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參數資料
| 型號： | X9241AUPI |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數字電位計 |
| 英文描述： | Low Powr/2-Wire Serial Bus |
| 中文描述： | QUAD 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數： | 11/18頁 |
| 文件大?。?/td> | 364K |
| 代理商： | X9241AUPI |
X9241A
Characteristics subject to change without notice.
11 of 18
REV 1.1.13 12/09/02
www.xicor.com
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Notes:
(1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten-
tiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R
H
–R
L
)/63, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP REQUIREMENTS
(Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First Vcc, then the potentiometer pins. It is suggested that Vcc
reach 90% of its final value before power is applied to the potentiometer pins. The Vcc ramp rate specification
should be met, and any glitches or slope changes in the Vcc line should be held to <100mV if possible. Also, Vcc
should not reverse polarity by more than 0.5V.
Notes:
(5) This parameter is guaranteed by characterization or sample testing.
(6) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are guaranteed by design.
(7) This parameter is guaranteed by design.
(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse
width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure
to the device.
Symbol
l
CC
Parameter
Limits
Typ.
Unit
mA
Test Condition
f
SCL
= 100kHz, SDA = Open,
Other Inputs = V
SS
SCL = SDA = V
CC
, Addr. = V
SS
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
Min.
Max.
3
Supply current (active)
I
SB
I
LI
I
LO
V
IH
V
IL
V
OL
V
CC
current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
200
500
10
10
μA
μA
μA
V
V
V
2
–1
V
CC
+ 1
0.8
0.4
I
OL
= 3mA
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
Symbol
C
I/O
(5)
C
IN
(5)
Parameter
Max.
19
12
Unit
pF
pF
Test Condition
V
I/O
= 0V
V
IN
= 0V
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
Symbol
t
PUR
(6)
t
PUW
(6)
t
R
V
CC
Parameter
Min.
Typ.
Max.
1
5
50
Unit
ms
ms
V/msec
Power-up to initiation of read operation
Power-up to initiation of write operation
V
CC
Power up ramp rate
0.2
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