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參數(shù)資料
| 型號： | X9241AYPM |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP QUAD 4X2K EE 20-DIP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | XDCP™ |
| 接片： | 64 |
| 電阻（歐姆）： | 2k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
4
FN8164.6
August 31, 2007
Principles of Operation
The X9241A is a highly integrated microcircuit incorporating
four resistor arrays, their associated registers and counters
and the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
Serial Interface
The X9241A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9241A will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (tLOW). SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (tHIGH). The X9241A continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8-bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the 8-bits of data. See Figure 7.
The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9241A will
respond with a final acknowledge.
Array Description
The X9241A is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (VH/RH
and VL/RL inputs).
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (VW/RW)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 6 least significant bits of
the WCR are decoded to select, and enable, 1 of 64
switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
4-bits of the slave address are the device type identifier
(refer to Figure 1). For the X9241A, this is fixed as 0101[B].
The next 4-bits of the slave address are the device address.
The physical device address is defined by the state of the A0
to A3 inputs. The X9241A compares the serial data stream
with the address input state; a successful compare of all 4
address bits is required for the X9241A to respond with an
acknowledge.
Acknowledge Polling
The disabling of the inputs, during the internal nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command,
the X9241A initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9241A is still busy with the write operation, no ACK will be
returned. If the X9241A has completed the write operation,
an ACK will be returned and the master can then proceed
with the next operation.
1
0
A3
A2
A1
A0
DEVICE TYPE
IDENTIFIER
DEVICE ADDRESS
1
FIGURE 1. SLAVE ADDRESS
X9241A
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