Power-up Requirements (Power Up sequencing can affect correct recall of the wiper " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� X9241AYSIZT1
寤犲晢锛� Intersil
鏂囦欢闋佹暩(sh霉)锛� 3/16闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC XDCP QUAD 4X2K EE 20-SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
绯诲垪锛� XDCP™
鎺ョ墖锛� 64
闆婚樆锛堟瓙濮嗭級锛� 2k
闆昏矾鏁�(sh霉)锛� 4
婧害绯绘暩(sh霉)锛� 妯�(bi膩o)婧�(zh菙n)鍊� ±300 ppm/°C
瀛樺劜鍣ㄩ鍨嬶細 闈炴槗澶�
鎺ュ彛锛� I²C锛堣ō(sh猫)鍌欎綅鍧€锛�
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 20-SOIC锛�0.295"锛�7.50mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-SOIC W
鍖呰锛� 甯跺嵎 (TR)
11
FN8164.6
August 31, 2007
Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then the potentiometer pins. It is suggested that Vcc reach 90% of its
final value before power is applied to the potentiometer pins. The VCC ramp rate specification should be met, and any glitches or
slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V.
NOTES:
7. Limits should be considered typical and are not production tested.
8. Limits established by characterization and are not production tested.
9. Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
10. Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse width that
is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device.
11. Parts are 100% tested at either +70掳C or +85掳C. Over temperature limits established by characterization and are not production tested.
Symbol Table
Endurance and Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
Capacitance
SYMBOL
PARAMETER
TEST CONDITION
TYP
UNIT
CI/O (Note 7)
Input/output capacitance (SDA)
VI/O = 0V
19
pF
CIN (Note 7)
Input capacitance (A0, A1, A2, A3 and SCL)
VIN = 0V
12
pF
Power-up Timing
SYMBOL
PARAMETER
MIN
(Note 11)
TYP
MAX
(Note 11)
UNIT
tPUR (Note 8)
Power-up to initiation of read operation
1
ms
tPUW (Note 8)
Power-up to initiation of write operation
5
ms
tRVCC
VCC Power up ramp rate
0.2
50
V/ms
AC Conditions of Test
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing levels
VCC x 0.5
Input pulse levels
VCC x 0.1 to VCC x 0.9
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don鈥檛 Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X9241A
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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X9241AYST1 鍔熻兘鎻忚堪:IC XDCP QUAD 4X2K EE 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:XDCP™ 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:XDCP™ 鎺ョ墖:256 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� ±300 ppm/°C 瀛樺劜鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:I²C锛堣ō(sh猫)鍌欎綅鍧€锛� 闆绘簮闆诲:2.7 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-TSSOP 鍖呰:甯跺嵎 (TR)
X9241AYSZ 鍔熻兘鎻忚堪:IC XDCP QUAD 4X2K EE 20-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:XDCP™ 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 鎺ョ墖:256 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):2 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 35 ppm/°C 瀛樺劜鍣ㄩ鍨�:鏄撳け 鎺ュ彛:6 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.6 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-TSSOP 鍖呰:甯跺嵎 (TR)
X9241AYSZT1 鍔熻兘鎻忚堪:IC XDCP QUAD 4X2K EE 20-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:XDCP™ 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 鎺ョ墖:256 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):2 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 35 ppm/°C 瀛樺劜鍣ㄩ鍨�:鏄撳け 鎺ュ彛:6 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.6 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-TSSOP 鍖呰:甯跺嵎 (TR)
X9241AYV 鍔熻兘鎻忚堪:IC XDCP QUAD 4X2K EE 20-TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:XDCP™ 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:XDCP™ 鎺ョ墖:256 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� ±300 ppm/°C 瀛樺劜鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:I²C锛堣ō(sh猫)鍌欎綅鍧€锛� 闆绘簮闆诲:2.7 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-TSSOP 鍖呰:甯跺嵎 (TR)
X9241AYVI 鍔熻兘鎻忚堪:IC XDCP QUAD 4X2K EE 20-TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:XDCP™ 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:XDCP™ 鎺ョ墖:256 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� ±300 ppm/°C 瀛樺劜鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:I²C锛堣ō(sh猫)鍌欎綅鍧€锛� 闆绘簮闆诲:2.7 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-TSSOP 鍖呰:甯跺嵎 (TR)