參數資料
| 型號： | X9251TP24I |
| 廠商： | Intersil |
| 文件頁數： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP QUAD 256TAP 100K 24-DIP |
| 標準包裝： | 30 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數： | 4 |
| 溫度系數： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 6 線 SPI（芯片選擇，設備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 包裝： | 管件 |
5
FN8166.5
April 13, 2007
One of Four Potentiometers
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW (i.e., VCC ≥ VH, VL,
VW). The VCC ramp rate specification is always in effect.
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction (See
Instruction section for more details). Finally, it is loaded with
the contents of its Data Register zero (DR#0) upon
power-up. (See Figure 1)
The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR#.
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Counter Register. All
operations changing data in one of the Data Registers is a
non-volatile operation and takes a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~ 255).
Status Register (SR)
This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.
When WIP = 1, indicates that high-voltage write cycle is in
progress.
When WIP = 0, indicates that no high-voltage write cycle is
in progress.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
8
COUNTER
IF WCR = 00[H] then RW is closet to RL
IF WCR = FF[H] then RW is closet to RH
WIPER
(WCR#)
#: 0, 1, 2, or 3
DR#2
DR#1
DR#3
- - -
DECODE
DCP
CORE
RW
RH
RL
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
X9251
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