參數(shù)資料
型號: X9251TS24I
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Single Supply/Low Power/256-Tap/SPI Bus
中文描述: QUAD 100K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: 0.300 INCH, PLASTIC, MS-013AD, SOIC-24
文件頁數(shù): 13/25頁
文件大小: 549K
代理商: X9251TS24I
X9251
Characteristics subject to change without notice.
13 of 25
REV 1.3.3 2/10/04
www.xicor.com
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Notes:
(1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Wiper Position
(Sent by X9251 on SO)
W
C
R
6
5
4
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 1
0
0
1
0
0
0
0
W
C
R
7
W
C
R
W
C
R
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by Host on SI)
W
C
R
6
5
4
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 1
0
1
0
0
0
0
0
W
C
R
7
W
C
R
W
C
R
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
1 RB RA P1 P0 D
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 1
0
1
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
Rising
Edge
H
W
0
1
0
1
0 0 A1 A0 1 1 0 0 RB RA P1 P0 D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
Falling
Edge
Device Type
Identifier
0
1
Device
Addresses
0
Instruction
Opcode
0
DR
Addresses
RB RA
CS
Rising
Edge
0
1
0
A1 A0 0
0
1
0
0
相關PDF資料
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X9251TS24I-2.7 Single Supply/Low Power/256-Tap/SPI Bus
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