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參數(shù)資料
| 型號： | X9251TV24 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally-Controlled (XDCP) Potentiometer |
| 中文描述： | 四數(shù)字控制（數(shù)字電位器）電位 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大小： | 549K |
| 代理商： | X9251TV24 |
X9251
Characteristics subject to change without notice.
8 of 25
REV 1.3.3 2/10/04
www.xicor.com
SERIAL INTERFACE
The X9251 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in, on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
I
DENTIFICATION
B
YTE
The first byte sent to the X9251 from the host, following
a CS going HIGH to LOW, is called the Identification
Byte. The most significant four bits of the Identification
Byte are a Device Type Identifier, ID[3:0]. For the
X9251, this is fixed as 0101 (refer to Table 3).
The least significant four bits of the Identification Byte
are the Slave Address bits, AD[3:0]. For the X9251, A3
is 0, A2 is 0, A1 is the logic value at the input pin A1,
and A0 is the logic value at the input pin A0. Only the
device which Slave Address matches the incoming
bits sent by the master executes the instruction. The
A1 and A0 inputs can be actively driven by CMOS
input signals or tied to V
CC
or V
SS
.
I
NSTRUCTION
B
YTE
The next byte sent to the X9251 contains the
instruction and register pointer information. The four
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least two significant bits point to one of four Wiper
Counter Registers or DCPs.The format is shown below
in Table 4.
Table 3. Identification Byte Format
Table 4. Instruction Byte Format
Data Register Selection
#: 0, 1, 2, or 3
Register
DR#0
DR#1
DR#2
DR#3
RB
0
0
1
1
RA
0
1
0
1
ID3
0
ID2
1
ID1
0
ID0
1
A3
0
A2
0
A1
A0
Pin A1
Logic Value
Pin A0
Logic Value
(LSB)
(MSB)
Device Type
Identifier
Slave Address
I3
I2
I1
I0
RB
RA
P1
P0
(MSB)
(LSB)
Instruction
Opcode
Register
Selection
DCP Selection
(WCR Selection)
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| X9251UV24-2.7 | Standard Recovery Power Rectifier; Gate Trigger Current Max, Igt:35mA; Forward Current:40A; Leaded Process Compatible:Yes; Mounting Type:PCB Thru Hole; Package/Case:TO-220AB; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
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| X9251UV24I-2.7 | Quad Digitally-Controlled (XDCP) Potentiometer |
| X9251TV24I-2.7 | Quad Digitally-Controlled (XDCP) Potentiometer |
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|---|---|
| X9251TV24-2.7 | 功能描述:IC XDCP QUAD 256TAP 100K 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9251TV24I | 功能描述:IC XDCP QUAD 256TAP 100K 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9251TV24I-2.7 | 功能描述:IC XDCP QUAD 256TAP 100K 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9251TV24IZ | 功能描述:IC XDCP QUAD 256TAP 100K 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲器類型:易失 接口:6 線串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
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