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參數(shù)資料
| 型號： | X9251US24 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DCP QUAD 50K 256TP 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 6 線 SPI（芯片選擇，設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC |
| 包裝： | 管件 |
7
FN8166.5
April 13, 2007
Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
Read Wiper Counter Register – read the current wiper
position of the selected potentiometer,
Write Wiper Counter Register – change current wiper
position of the selected potentiometer,
Read Data Register – read the contents of the selected
Data Register,
Write Data Register – write a new value to the selected
Data Register,
Read Status – this command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action is delayed by tWRL. A transfer from the WCR
(current wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of tWR to complete.
The transfer can occur between one of the four
potentiometer’s WCR, and one of its associated registers,
DRs; or it may occur globally, where the transfer occurs
between all potentiometers and one associated register. The
Read Status Register instruction is the only unique format
(See Figure 5).
Four instructions require a two-byte sequence to complete.
These instructions transfer data between the host and the
X9251; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are:
XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
TABLE 5. INSTRUCTION SET
INSTRUCTION
INSTRUCTION SET
OPERATION
I3
I2
I1
I0
RB
RA
P1
P0
Read Wiper Counter Register
1
0
1
0
1/0
Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter Register
1
0
1
0
1/0
Write new value to the Wiper Counter
Register pointed to by P1 - P0
Read Data Register
1
0
1
1/0
Read the contents of the Data Register pointed to
by P1 - P0 and RB - RA
Write Data Register
1
0
1/0
Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to
Wiper Counter Register
1
0
1
1/0
Transfer the contents of the Data Register pointed to
by P1 - P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
0
1/0
Transfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Data Register pointed
to by RB - RA
Global XFR Data Registers to
Wiper Counter Registers
0
1
1/0
0
Transfer the contents of the Data Registers pointed
to by RB - RA of all four pots to their respective
Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
1
0
1/0
0
Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed
to by RB - RA of all four pots
Increment/Decrement
Wiper Counter Register
0
1
0
1/0
Enable Increment/decrement of the Control Latch
pointed to by P1 - P0
NOTE: 1/0 = data is one or zero
X9251
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| X9251US24-2.7 | 功能描述:IC DCP QUAD 50K 256TP 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9251US24-2.7T1 | 功能描述:IC XDCP QUAD 256TAP 50K 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9251US24I | 功能描述:IC DCP QUAD 50K 256TP 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9251US24I-2.7 | 功能描述:IC DCP QUAD 50K 256TP 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9251US24I-2.7T1 | 功能描述:IC XDCP QUAD 256TAP 50K 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
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