FN8167.2 November 14, 2005 Serial Acknowledge An ACK (Acknowledge), is a software convention used to indicate a successful data transfer" />
參數(shù)資料
型號(hào)： X9252TV24IZ-2.7
廠商： Intersil
文件頁(yè)數(shù)： 2/20頁(yè)
文件大?。?/td> 0K
描述： IC POT DGTL QUAD 100KOHM 24TSSOP
標(biāo)準(zhǔn)包裝： 62
系列： XDCP™
接片： 256
電阻（歐姆）： 100k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型： 非易失
接口： I²C（芯片選擇，設(shè)備位址，增/減）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
10
FN8167.2
November 14, 2005
Serial Acknowledge
An ACK (Acknowledge), is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits
of data (See Figure 3).
The device responds with an ACK after recognition of a
START condition followed by a valid Slave Address byte. A
valid Slave Address byte must contain the Device Type
Identifier 0101, and the Device Address bits matching the
logic state of pins A2, A1, and A0 (See Figure 4).
If a write operation is selected, the device responds with an
ACK after the receipt of each subsequent eight-bit word.
In the read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.
Slave Address Byte
Following a START condition, the master must output a Slave
Address Byte (Refer to figure 4.). This byte includes three parts:
- The four MSBs (SA7-SA4) are the Device Type Identifier,
which must always be set to 0101 in order to select the
X9252.
- The next three bits (SA3-SA1) are the Device Address bits
(AS2-AS0). To access any part of the X9252’s memory,
the value of bits AS2, AS1, and AS0 must correspond to
the logic levels at pins A2, A1, and A0 respectively.
- The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being
addressed. When the R/W bit is “1”, then a Read
operation is selected. A “0” selects a Write operation
.
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
SDA Output from
Transmitter
SDA Output from
Receiver
8
1
9
START
ACK
SCL from Master
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
SA6
SA7
SA5
SA3
SA2
SA1
SA0
Device Type
Identifier
Read or
SA4
SLAVE ADDRESS
BIT(S)
DESCRIPTION
SA7-SA4
Device Type Identifier
SA3-SA1
Device Address
SA0
Read or Write Operation Select
R/W
01
0
1
Address
Device
AS0
AS1
AS2
Write
FIGURE 4. SLAVE ADDRESS (SA) FORMAT
X9252
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