FN8167.2 November 14, 2005 IL Leakage current, bus interface pins Voltage at pin" />
參數(shù)資料
型號(hào): X9252WV24IZ-2.7
廠商: Intersil
文件頁(yè)數(shù): 16/20頁(yè)
文件大小: 0K
描述: IC POT DGTL QUAD 24-TSSOP
標(biāo)準(zhǔn)包裝: 62
系列: XDCP™
接片: 256
電阻(歐姆): 10k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型: 非易失
接口: I²C(芯片選擇,設(shè)備位址,增/減)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1237 (CN2011-ZH PDF)
5
FN8167.2
November 14, 2005
IL
Leakage current, bus interface pins
Voltage at pin from VSS to VCC
-10
10
A
VIH
Input HIGH voltage
VCC x 0.7 VCC + 1
V
VIL
Input LOW voltage
-1
VCC x 0.3
V
VOL
SDA pin output LOW voltage
IOL = 3mA
0.4
V
DC Electrical Specifications
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
Endurance and Data Retention
PARAMETER
MIN
UNITS
Minimum endurance
100,000
Data changes per bit
Data retention
100
Years
Capacitance
Symbol
Test
Test Conditions
Max.
Units
CIN/OUT (Note 5) Input / Output capacitance (SDA)
VOUT = 0V
8
pF
CIN (Note 5)
Input capacitance (SCL, WP, DS0, DS1, CS, U/D, A2, A1 and
A0)
VIN = 0V
6
pF
Power-Up Timing
SYMBOL
PARAMETER
MAX
UNITS
tD (Notes 5, 9)
Power Up Delay from VCC power up (VCC above 2.7V) to wiper position recall
completed, and communication interfaces ready for operation.
2ms
A.C. Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing threshold level
VCC x 0.5
External load at pin SDA
2.3k
to VCC and 100pF to VSS
2-Wire Interface timing (s)
SYMBOL
PARAMETER
MIN
MAX
UNITS
fSCL
Clock Frequency
400
kHz
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Condition Setup Time
600
ns
tHD:STA
Start Condition Hold Time
600
ns
tSU:STO
Stop Condition Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time
30
ns
tR (Note 5)
SCL and SDA Rise Time
300
ns
tF (Note 5)
SCL and SDA Fall Time
300
ns
tAA (Note 5)
SCL Low to SDA Data Output Valid Time
0.9
s
tDH
SDA Data Output Hold Time
0
ns
tIN (Note 5)
Pulse Width Suppression Time at SCL and SDA inputs
50
ns
X9252
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