參數(shù)資料
型號: X9258TS24I
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Low Noise/Low Power/2-Wire Bus/256 Taps
中文描述: QUAD 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: 0.300 INCH, PLASTIC, MS-013ADC, SOIC-24
文件頁數(shù): 2/22頁
文件大?。?/td> 413K
代理商: X9258TS24I
X9258
Characteristics subject to change without notice.
2 of 22
REV 1.1.7 2/4/03
www.xicor.com
PIN DESCRIPTIONS
Host Interface Pins
S
ERIAL
C
LOCK
(SCL)
The SCL input is used to clock data into and out of the
X9258.
S
ERIAL
D
ATA
(SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
D
EVICE
A
DDRESS
(A
0
A
3
)
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with
the
address
input
communication with the X9258. A maximum of 16
devices may occupy the 2-wire serial bus.
in
order
to
initiate
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
–V
H3
/R
/R
H3
inputs are equivalent to the
), V
L
/R
L
(V
L0
/R
L0
–V
L3
/R
L3
)
The V
terminal connections on either end of a mechanical
potentiometer.
H
/R
H
and V
L
L
V
W
/R
W
(V
W0
/R
W0
–V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages
for the DCP analog section.
PIN CONFIGURATION
NC
A0
V
W3
/R
W3
V
H3
/R
H3
V
L3
/R
L3
V+
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
14
A3
SCL
V
L2
/R
L2
V
H2
/R
H2
V
W2
/R
W2
V–
V
SS
V
W1
/R
W1
V
H1
/R
H1
V
L1
/R
L1
A1
SOIC/TSSOP
X9258
13
11
12
A2
SDA
WP
2
3
4
A
B
C
D
E
F
Top View–Bumps Down
R
W0
R
L0
V+
A
0
A
3
R
L1
V
CC
R
L3
R
W3
NC
SDA
R
W1
SCL
R
L2
WP
V-
R
H0
R
H1
R
H3
V
SS
R
W2
A
2
A
1
1
CSP
R
H2
相關PDF資料
PDF描述
X9258US24 Low Noise/Low Power/2-Wire Bus/256 Taps
X9258US24-2.7 Low Noise/Low Power/2-Wire Bus/256 Taps
X9258US24I Low Noise/Low Power/2-Wire Bus/256 Taps
X9258US24I-2.7 Low Noise/Low Power/2-Wire Bus/256 Taps
X9258UV24 Low Noise/Low Power/2-Wire Bus/256 Taps
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