參數(shù)資料
| 型號： | X9258TS24IZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP QUAD 256TP 100K 24-SOIC |
| 標準包裝： | 1,000 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC |
| 包裝： | 帶卷 (TR) |
4
FN8168.6
December 15, 2011
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (tLOW). SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (tHIGH). The X9258 continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8 bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the 8 bits of data.
The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte, the X9258 will
respond with a final acknowledge.
Array Description
The X9258 is comprised of four resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (VH/RH
and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (VW)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 8 bits of the WCR are
decoded to select, and enable, one of 256 switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated data
registers into the WCR. These data registers and the WCR
can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
4 bits of the slave address are the device type identifier
(refer to Figure 1). For the X9258 this is fixed as 0101[B].
The next 4 bits of the slave address are the device address.
The physical device address is defined by the state of the A0
thru A3 inputs. The X9258 compares the serial data stream
with the address input state; a successful compare of all
4 address bits is required for the X9258 to respond with an
acknowledge. The A0 thru A3 inputs can be actively driven
by CMOS input signals or tied to VCC or VSS.
Acknowledge Polling
The disabling of the inputs (during the internal nonvolatile
write operation), can be used to take advantage of the
typical 5ms nonvolatile write cycle time. Once the stop
condition is issued to indicate the end of the nonvolatile write
command, the X9258 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If the
X9258 is still busy with the write operation, no ACK will be
returned. If the X9258 has completed the write operation an
ACK will be returned and the master can then proceed with
the next operation.
1
00
A3
A2
A1
A0
DEVICE TYPE
IDENTIFIER
DEVICE ADDRESS
1
FIGURE 1. SLAVE ADDRESS
X9258
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