參數(shù)資料
型號: X9258UV24I-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Low Noise/Low Power/2-Wire Bus/256 Taps
中文描述: QUAD 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: 4.40 MM, TSSOP-24
文件頁數(shù): 14/22頁
文件大?。?/td> 413K
代理商: X9258UV24I-2.7
X9258
Characteristics subject to change without notice.
14 of 22
REV 1.1.7 2/4/03
www.xicor.com
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Test Circuit #3 SPICE Macro Model
I
nput pulse levels
Input rise and fall times
Input and output timing level
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
5V
1533
100pF
SDA Output
2.7V
100pF
10pF
R
H
R
TOTAL
C
H
25pF
C
W
C
L
10pF
R
W
R
L
Macro Model
AC TIMING
(Over recommended operating condition)
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
f
SCL
t
CYC
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:STO
t
SU:DAT
t
HD:DAT
t
R
t
F
t
AA
t
DH
T
I
t
BUF
t
SU:WPA
t
HD:WPA
Parameter
Min.
Max.
400
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock frequency
Clock cycle time
Clock high time
Clock low time
Start setup time
Start hold time
Stop setup time
SDA data input setup time
SDA data input hold time
SCL and SDA rise time
SCL and SDA fall time
SCL low to SDA data output valid time
SDA data output hold time
Noise suppression time constant at SCL and SDA inputs
Bus free rime (prior to any transmission)
WP, A0, A1, A2 and A3 setup time
WP, A0, A1, A2 and A3 hold time
2500
600
1300
600
600
600
100
30
300
300
900
50
50
1300
0
0
Symbol
t
WR
Parameter
Typ.
5
Max.
10
Unit
ms
High-voltage write cycle time (store instructions)
相關(guān)PDF資料
PDF描述
X9258 Low Noise/Low Power/2-Wire Bus/256 Taps
X9258TS24I-2.7 Low Noise/Low Power/2-Wire Bus/256 Taps
X9258TV24 Low Noise/Low Power/2-Wire Bus/256 Taps
X9258TV24-2.7 Low Noise/Low Power/2-Wire Bus/256 Taps
X9258TV24I Low Noise/Low Power/2-Wire Bus/256 Taps
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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X9258UV24Z-2.7 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers
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