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參數(shù)資料
| 型號： | X9269UV24IZ-2.7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP DUAL 256TAP 50K 24-TSSOP |
| 標準包裝： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 管件 |
8
FN8173.4
April 17, 2007
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9269
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9269 is still busy with the write operation no ACK
will be returned. If the X9269 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1: ACK Polling Sequence
INSTRUCTION AND REGISTER DESCRIPTION
Instructions
DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9269 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9269; this is fixed
as 0101[B] (refer to Table 1).
The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3-A0 input pins. The slave address
is externally specified by the user. The X9269
compares the serial data stream with the address
input state; a successful compare of both address
bits is required for the X9269 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to VCC or VSS.
INSTRUCTION BYTE (I)
The next byte sent to the X9269 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots. The format is shown in Table 2.
Register Selection
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction
Issue STOP
No
Yes
Proceed
Issue STOP
No
Proceed
Register Selected
RB
RA
DR0
0
DR1
0
1
DR2
1
0
DR3
1
X9269
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相關代理商/技術參數(shù) |
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| X9269UV24T1 | 功能描述:IC XDCP DUAL 256TAP 50K 24-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標準包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9271 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Single Supply/Low Power/256-Tap/SPI Bus |
| X9271-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Single Supply/Low Power/256-Tap/SPI Bus |
| X9271TB | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Single Digitally-Controlled (XDCP) Potentiometer |
| X9271TB-2.7 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Single Digitally-Controlled (XDCP) Potentiometer |
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