參數(shù)資料
型號(hào): X9271
元件分類: 數(shù)字電位計(jì)
英文描述: Single Digitally-Controlled (XDCP) Potentiometer
中文描述: 單數(shù)字控制(數(shù)字電位器)電位
文件頁數(shù): 5/23頁
文件大小: 403K
代理商: X9271
X9271
Characteristics subject to change without notice.
5 of 23
REV 1.1.7 2/6/03
www.xicor.com
PRINCIPLES OF OPERATION
Device Description
S
ERIAL
I
NTERFACE
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
A
RRAY
D
ESCRIPTION
The X9271 is comprised of a resistor array (see Figure
1). The array contains the equivalent of 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
inputs).
H
and R
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
P
OWER
U
P
AND
D
OWN
R
ECOMMENDATIONS
.
There are no restrictions on the power-up or power-
down conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
V
H
,
V
L
, V
W
. The V
CC
ramp rate specification is always in
effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
REGISTER 2
(DR2)
REGISTER 3
(DR3)
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
R
H
R
L
R
W
8
8
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN R
W
= R
L
IF WCR = FF[H] THEN R
W
= R
H
WIPER
BANK_0 Only
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