參數(shù)資料
型號: X9271UVI-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Single Supply/Low Power/256-Tap/SPI Bus
中文描述: 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
封裝: PLASTIC, TSSOP-14
文件頁數(shù): 10/23頁
文件大?。?/td> 403K
代理商: X9271UVI-2.7
X9271
Characteristics subject to change without notice.
10 of 23
REV 1.1.7 2/6/03
www.xicor.com
Figure 5. Increment/Decrement Instruction Sequence
Figure 6. Increment/Decrement Timing Limits
Table 6. Instruction Set
Note:
1/0 = data is one or zero
Instruction
Instruction Set
I1
I0
0
1
Operation
I3
1
I2
0
RB
0
RA
0
P
1
0
P
0
1/0
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
Read the contents of the Wiper Counter
Register
Write new value to the Wiper Counter
Register
Read the contents of the Data Register
pointed to by P1-P0 and RB-RA
Write new value to the Data Register
pointed to by P1-P0 and RB-RA
Transfer the contents of the Data Register
pointed to by RB-RA (Bank 0 only) to the
Wiper Counter Register
Transfer the contents of the Wiper Counter
Register to the Register pointed to by RB-RA
(Bank 0 only)
Enable Increment/decrement of the Wiper
Counter Register
Read the status of the internal write cycle, by
checking the WIP bit.
1
0
1
0
0
0
0
1/0
1
0
1
1
1/0
1/0
1/0
1/0
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
XFR Data Register to
Wiper Counter Register
1
1
0
1
1/0
1/0
0
0
XFR Wiper Counter
Register to Data Register
1
1
1
0
1/0
1/0
0
0
Increment/Decrement
Wiper Counter Register
Read Status (WIP bit)
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
A1 A0
I3
I2
I1
I0
RA RB
P0
SCL
SI
CS
0
0
ID3 ID2 ID1 ID0
Device ID
Internal
Address
Instruction
Opcode
Register
Address
Pot/Bank
Address
0
0
P1
0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
SCK
SI
VW
INC/DEC CMD ISSUED
tWRID
VOLTAGE OUT
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