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參數(shù)資料
| 型號： | X9313ZS-3T2 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP 32-TAP 1K 3-WIRE 8-SOIC |
| 標準包裝： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 32 |
| 電阻（歐姆）： | 1k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 3 線串行（芯片選擇，遞增，增/減） |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8177.6
January 15, 2008
X9313
Plastic Dual-In-Line Packages (PDIP)
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
INCHES
TOLERANCE
NOTES
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
A
0.210
MAX
A1
0.015
MIN
A2
0.130
±0.005
b
0.018
±0.002
b2
0.060
+0.010/-0.015
c
0.010
+0.004/-0.002
D
0.375
0.750
0.890
1.020
±0.010
1
E
0.310
+0.015/-0.010
E1
0.250
±0.005
2
e
0.100
Basic
eA
0.300
Basic
eB
0.345
±0.025
L
0.125
±0.010
N
8
14
16
18
20
Reference
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
D
L
A
e
b
A1
NOTE 5
A2
SEATING
PLANE
L
N
PIN #1
INDEX
E1
12
N/2
b2
E
eB
eA
c
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| X9313ZSI-3T1 | 功能描述:IC XDCP 32-TAP 1K 3-WIRE 8-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標準值 50 ppm/°C 存儲器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細型，TSOT-23-6 供應商設備封裝:TSOT-23-6 包裝:帶卷 (TR) |
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