4
FN8181.2
February 19, 2008
Test Circuit #1
Circuit #2 SPICE Macro Model
ILI
CS
VCC = 5V, CS = 0
120
200
250
A
ILI
INC, U/D Input Leakage Current
VIN = VSS to VCC
±1
A
VIH
CS, INC, U/D Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
CS, INC, U/D Input LOW Voltage
-0.5
VCC x 0.1
V
CIN
CS, INC, U/D Input Capacitance
VCC = 5V, VIN = VSS, TA = +25°C,
f=1MHz
10
pF
DC Electrical Specifications
Over recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
Endurance and Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
200,000
Data changes per bit
Data retention
100
Years
VL
TEST POINT
VH/RH
AC Conditions of Test
Input pulse levels
0V to 5V
Input rise and fall times
10ns
Input reference levels
1.5V
CH
CL
10pF
RH
RTOTAL
CW
25pF
RL
AC Electrical Specifications
Over recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tCl
CS to INC Setup
100
ns
tlD
INC HIGH to U/D Change
100
ns
tDI
U/D to INC Setup
100
ns
tlL
INC LOW Period
1
s
tlH
INC HIGH Period
1
s
tlC
INC Inactive to CS Inactive
1
s
tCPH
CS Deselect Time (No Store)
250
ns
tCPH
CS Deselect Time (Store)
10
ms
tCYC
INC Cycle Time
2
s
tR, tF
INC Input Rise and Fall time
500
s
tR VCC
VCC Power-up Rate
1
50
V/ms
tWR
Store Cycle
510
ms
X93155