參數(shù)資料
型號: X9317WS8I-2.7T2
廠商: Intersil
文件頁數(shù): 3/13頁
文件大小: 0K
描述: IC XDCP SGL 100TAP 10K 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: XDCP™
接片: 100
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲器類型: 非易失
接口: 3 線串行(芯片選擇,遞增,增/減)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
11
FN8183.7
March 7, 2012
X9317
Package Outline Drawing
M8.173
8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 01/10
NOTES:
END VIEW
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
B
A
C
PLANE
SEATING
0.10 C
0.10
C B A
H
3.0 ±0.5
4.40 ±0.10
0.25 +0.05/-0.06
6.40
0.20 C B A
0.05
0°-8°
GAUGE
PLANE
SEE DETAIL "X"
0.90 +0.15/-0.10
0.60 ±0.15
0.09-0.20
6
3
4
2
4
1.00 REF
0.65
1.20 MAX
0.25
0.05 MIN
0.15 MAX
(5.65)
(0.65 TYP)
(0.35 TYP)
(1.45)
1
C
L
PIN 1
ID MARK
4
5
8
PACKAGE BODY
OUTLINE
SIDE VIEW
2. Dimension does not include mold flash, protrusions or
gate burrs. Mold flash, protrusions or gate burrs shall
3. Dimension does not include interlead flash or protrusion.
Interlead flash or protrusion shall not exceed 0.15 per side.
4. Dimensions are measured at datum plane H.
not exceed 0.15 per side.
5. Dimensioning and tolerancing per ASME Y14.5M-1994.
6. Dimension on lead width does not include dambar protrusion.
Allowable protrusion shall be 0.08 mm total in excess of
dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm.
7. Conforms to JEDEC MO-153, variation AC. Issue E
Dimensions in (
) for Reference Only.
1. Dimensions are in millimeters.
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