參數(shù)資料
型號(hào): X9400
廠商: Intersil Corporation
英文描述: Low Noise/Low Power/SPI Bus
中文描述: 低噪音/低功耗/ SPI總線
文件頁(yè)數(shù): 8/22頁(yè)
文件大?。?/td> 150K
代理商: X9400
X9400
Characteristics subject to change without notice.
8 of 22
REV 1.1.4 10/11/02
www.xicor.com
Instruction Format
Notes:
(1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
Write Wiper Counter Register (WCR)
device type
identifier
Read Data Register (DR)
device type
identifier
Write Data Register (DR)
device type
identifier
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
addresses
A
1
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
addresses
A
1
0
CS
Falling
Edge
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9400 on SO)
W
P
5
4
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
1
0
0
1
0
0
P
1
P
0
0
0
W
P
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
W
P
5
4
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
1
0
1
0
0
0
P
1
P
0
0
0
W
P
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device
addresses
instruction
opcode
DR and WCR
addresses
Data Byte
(sent by X9400 on SO)
W
P
5
4
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
1
0
1
1
R
1
R
0
P
1
P
0
0
0
W
P
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device
addresses
instruction
opcode
DR and WCR
addresses
Data Byte
(sent by host on SI)
W
P
5
4
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1 0 0
A
1
A
0
1 1 0 0
R
1
R
0
P
1
P
0
0 0
W
P
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device
instruction
opcode
DR and WCR
addresses
R
1
0
CS
Rising
Edge
0 1 0 1 0 0
A
1 1 0 1
R
P
1
P
0
CS
Falling
Edge
device
instruction
opcode
DR and WCR
addresses
R
1
0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0
0
A
1
1
1
0
R
P
1
P
0
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