(5) t
參數(shù)資料
型號: X9400WP24
廠商: Intersil
文件頁數(shù): 5/19頁
文件大?。?/td> 0K
描述: IC DCP QUAD 10K 64TP 24DIP
標準包裝: 16
系列: XDCP™
接片: 64
電阻(歐姆): 10k
電路數(shù): 4
溫度系數(shù): 標準值 ±300 ppm/°C
存儲器類型: 非易失
接口: 6 線 SPI(芯片選擇,設備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
包裝: 管件
13
FN8189.3
July 28, 2006
A.C. TEST CONDITIONS
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) tPUR and tPUW are the delays required from the time the
third (last) power supply (VCC, V+ or V-) is stable until the
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
SPICE Macro Model
SYMBOL TABLE
AC TIMING
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Symbol
Parameter
Min.
Max.
Unit
fSCK
SSI/SPI clock frequency
2.0
MHz
tCYC
SSI/SPI clock cycle time
500
ns
tWH
SSI/SPI clock high time
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
s
tFI
SI, SCK, HOLD and CS input fall time
2
s
tDIS
SO output disable time
0
500
ns
tV
SO output valid time
100
ns
tHO
SO output hold time
0
ns
tRO
SO output rise time
50
ns
tFO
SO output fall time
50
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in High Z
100
ns
tLZ
HOLD high to output in Low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
20
ns
tCS
CS deselect time
2
s
tWPASU
WP, A0 and A1 setup time
0
ns
tWPAH
WP, A0 and A1 hold time
0
ns
X9400
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