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參數(shù)資料
型號(hào)： X9400YV24IZ-2.7
廠商： Intersil
文件頁(yè)數(shù)： 16/19頁(yè)
文件大小： 0K
描述： IC XDCP QUAD 64-TAP 2.5K 24TSSOP
標(biāo)準(zhǔn)包裝： 62
系列： XDCP™
接片： 64
電阻（歐姆）： 2.5k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 6 線 SPI（芯片選擇，設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
6
FN8189.3
July 28, 2006
Figure 3. Instruction Byte Format
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P0) selects which one of the four
potentiometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register —
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter Register
—This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Register
—This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where the
transfer occurs between all potentiometers and one
associated register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The sequence of these operations is shown in Figure 5
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
I1
I2
I3
I0
R1
R0
P1
P0
Pot Select
Register
Select
Instructions
X9400
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