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參數(shù)資料
| 型號： | X9408WV24ZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP QUAD 64-TAP 10K 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 64 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
12
FN8191.4
January 15, 2009
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
3. MI = RTOT/63 or [V(VH/RH) - V(VL/RL)]/63, single pot
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
NOTES:
4. Limits should be considered typical and are not production tested.
5. tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
DC Electrical Specifications
(Over recommended operating conditions unless otherwise stated.
)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN
(Note 6)
TYP
(Note 4)
MAX
(Note 6)
UNIT
ICC1
VCC supply current (nonvolatile write)
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
5mA
ICC2
VCC supply current (move wiper, write,
read)
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
250
A
ISB
VCC current (standby)
SCL = SDA = VCC, Addr. = VSS
3A
ILI
Input leakage current
10
A
ILO
Output leakage current
10
A
VIH
Input HIGH voltage
VCC x 0.7
VCC +0.5
V
VIL
Input LOW voltage
–0.5
VCC x 0.1
V
VOL
Output LOW voltage
IOL = 3mA
0.4
V
PARAMETER
MIN
UNIT
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
SYMBOL
TEST
TEST CONDITION
TYP
(Note 4)
UNIT
Input/output capacitance (SDA)
VI/O = 0V
8
pF
Input capacitance (A0, A1, A2, A3, and SCL)
VIN = 0V
6
pF
SYMBOL
PARAMETER
MIN
(Note 6)
MAX
(Note 6)
UNIT
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
5
ms
VCC Power-up Ramp
0.2
50
V/msec
X9408
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