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參數(shù)資料
| 型號： | X9408YV24ZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP QUAD 64-TAP 2.5K 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 64 |
| 電阻（歐姆）： | 2.5k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
13
FN8191.4
January 15, 2009
Power-up Requirements
(Power-up sequencing can affect correct recall of the wiper
registers).
The preferred power-on sequence is as follows: First V-,
then VCC and V+, and then the potentiometer pins, VH/RH,
VL/RL, and VW/RW. Voltage should not be applied to the
potentiometer pins before V+ or V- is applied. The VCC ramp
rate specification should be met, and any glitches or slope
changes in the VCC line should be held to <100mV if
possible. If VCC powers down, it should be held below 0.1V
for more than 1 second before powering up again in order for
proper wiper register recall. Also, VCC should not reverse
polarity by more than 0.5V. Recall of wiper position will not
be complete until VCC, V+ and V- reach their final value.
A.C. Test Conditions
Equivalent A.C. Load Circuit
Circuit #3 SPICE Macro Model
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
5V
1533
Ω
100PF
SDA OUTPUT
10pF
VH/RH
RTOTAL
CH
25pF
CW
CL
10pF
VW/RW
VL/RL
X9408
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| X9409 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digitally Controlled Potentiometers |
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