參數(shù)資料
型號(hào): X9409WS24IZT1
廠商: Intersil
文件頁(yè)數(shù): 16/20頁(yè)
文件大?。?/td> 0K
描述: IC XDCP QUAD 64-TAP 10K 24-SOIC
標(biāo)準(zhǔn)包裝: 1,000
系列: XDCP™
接片: 64
電阻(歐姆): 10k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 帶卷 (TR)
5
FN8192.4
October 12, 2006
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed tWRL. A transfer from the Wiper
Counter Register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9409; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected Data
Register). The sequence of operations is shown in
Figure 4.
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9409 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the VH/RH
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
Table 1. Instruction Set
Note: (7) 1/0 = data is one or zero
Instruction
Instruction Set
Operation
I3
I2
I1
I0 R1 R0
P1
P0
Read Wiper Counter
Register
1
0010
0
P1
P0 Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter
Register
1
0100
0
P1
P0 Write new value to the Wiper Counter Register
pointed to by P1 - P0
Read Data Register
1
0
1
R1
R0
P1
P0 Read the contents of the Data Register pointed to
by P1 - P0 and R1 - R0
Write Data Register
1
0
R1
R0
P1
P0 Write new value to the Data Register pointed to
by P1 - P0 and R1 - R0
XFR Data Register to
Wiper Counter Register
1
101
R1
R0
P1
P0 Transfer the contents of the Data Register
pointed to by P1 - P0 and R1 - R0 to its associated
Wiper Counter Register
XFR Wiper Counter
Register to Data
Register
1
110
R1
R0
P1
P0 Transfer the contents of the Wiper Counter
Register pointed to by P1 - P0 to the Data
Register pointed to by R1 - R0
Global XFR Data
Registers to Wiper
Counter Registers
0
001
R1
R0
0
Transfer the contents of the Data Registers
pointed to by R1 - R0 of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper
Counter Registers to
Data Register
1
000
R1
R0
0
Transfer the contents of both Wiper Counter
Registers to their respective Data Registers
pointed to by R1 - R0 of all four pots
Increment/Decrement
Wiper Counter Register
0
0100
0
P1
P0 Enable Increment/decrement of the WCR Latch
pointed to by P1 - P0
X9409
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