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參數(shù)資料
| 型號： | X9410WP24 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP DUAL 64-TAP 10K 24-DIP |
| 標準包裝： | 16 |
| 系列： | XDCP™ |
| 接片： | 64 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 6 線 SPI（芯片選擇，設備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.600"，15.24mm） |
| 供應商設備封裝： | 24-PDIP |
| 包裝： | 管件 |
5
FN8193.2
October 12, 2006
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9410 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9410 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9410 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9410 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the ID byte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9410 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 3.
Figure 3. Instruction Byte Format
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P0)
selects which one of the two potentiometers is to be
affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Counter Register—This
transfers the contents of both specified Data Registers
to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data
Register—This transfers the contents of both Wiper
Counter Registers to the specified associated Data
Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between both potentiometers and
one associated register.
1
00
0
A1
A0
Device Type
Identifier
Device Address
1
I1
I2
I3
I0
R1
R0
0
P0
Pot Select
Register
Select
Instructions
X9410
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| X9410WP24-2.7 | 功能描述:IC XDCP DUAL 64-TAP 10K 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標準值 50 ppm/°C 存儲器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細型，TSOT-23-6 供應商設備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| X9410WP24I | 功能描述:IC XDCP DUAL 64-TAP 10K 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標準值 50 ppm/°C 存儲器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細型，TSOT-23-6 供應商設備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| X9410WP24I-2.7 | 功能描述:IC XDCP DUAL 64-TAP 10K 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標準值 50 ppm/°C 存儲器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細型，TSOT-23-6 供應商設備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| X9410WP24M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Potentiometer |
| X9410WP24M-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Potentiometer |
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