參數(shù)資料
型號(hào): X9410WV24IZ-2.7
廠(chǎng)商: Intersil
文件頁(yè)數(shù): 18/21頁(yè)
文件大?。?/td> 0K
描述: IC XDCP DUAL 64-TAP 10K 24-TSSOP
標(biāo)準(zhǔn)包裝: 62
系列: XDCP™
接片: 64
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類(lèi)型: 非易失
接口: 6 線(xiàn) SPI(芯片選擇,設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
6
FN8193.2
October 12, 2006
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9410; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The sequence of these operations is shown in Figure 5
The final command is Increment/Decrement. It is
different from the other commands because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps, thereby providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figure 7 and Figure 8.
Figure 4. Two-Byte Instruction Sequence
Figure 5. Three-Byte Instruction Sequence (Write)
Figure 6. Three-Byte Instruction Sequence (Read)
0101
00A1 A0
I3
I2
I1
I0
R1 R0
0 P0
SCK
SI
CS
0
1
0
1
A1 A0
I3
I2
I1 I0
R1 R0 0 P0
SCL
SI
0
D5 D4 D3 D2 D1 D0
CS
00
0
1
0
1
A1 A0
I3
I2
I1 I0
R1 R0 0
P0
SCL
SI
CS
00
S0
0
D5 D4 D3 D2 D1 D0
Don’t Care
X9410
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