參數(shù)資料
型號: X9420WSI
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Single Digitally Controlled (XDCP) Potentiometer
中文描述: 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16
封裝: 0.300 INCH, PLASTIC, SOIC-16
文件頁數(shù): 8/20頁
文件大?。?/td> 113K
代理商: X9420WSI
X9420
Characteristics subject to change without notice.
8 of 20
REV 1.1.6 7/30/02
www.xicor.com
Instruction Format
Notes:
(1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Read the contents of the Register pointed to by R1-R0.
Write Data Register (DR)
Write a new value to the Register pointed to by R1-R0.
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1-R0 to the WCR.
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
wiper position
(sent by X9420 on SO)
W
P
5
4
CS
Rising
Edge
0
1
0
1
1
1
0
A
0
1
0
0
1
0
0
0
0
0
0
W
P
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by Host on SI)
W
P
5
4
CS
Rising
Edge
0
1
0
1
1
1
0
A
0
1
0
1
0
0
0
0
0
0
0
W
P
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by X9420 on SO)
W
P
5
4
CS
Rising
Edge
0
1
0
1
1
1
0
A
0
1
0
1
1
R
1
R
0
0
0
0
0
W
P
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by host on SI)
W
P
5
4
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1 1 1 0
A
0
1 1 0 0
R
1
R
0
0 0 0 0
W
P
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses
R
1
0
CS
Rising
Edge
0 1 0 1 1 1 0
A
0
1 1 0 1
R
0 0
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