參數(shù)資料
型號: X9420WVI-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Single Digitally Controlled (XDCP) Potentiometer
中文描述: 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO14
封裝: PLASTIC, TSSOP-14
文件頁數(shù): 5/20頁
文件大?。?/td> 113K
代理商: X9420WVI-2.7
X9420
Characteristics subject to change without notice.
5 of 20
REV 1.1.6 7/30/02
www.xicor.com
The four high order bits of the instruction byte specify
the operation. The next two bits (R
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
are defined as 0.
1
and R
0
) select one
Two of the eight instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register —This
instruction transfers the contents of one specified
Data Register to the Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between the potentiometer and one of its associated
registers.
WRL
. A transfer
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9420; either between the host and one
of the Data Registers or directly between the host and
the WCR. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the pot,
– Write Wiper Counter Register—change current wiper
position of the pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (t
while SI is HIGH, the selected wiper will move one
resistor segment towards the V
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the
V
L
/R
L
terminal. A detailed illustration of the sequence
and timing for this operation are shown in Figure 7 and
Figure 8.
HIGH
)
H
/R
H
terminal. Similarly,
Figure 4. Two-Byte Instruction Sequence
0
1
0
1
1
1
0
A0
I3
I2
I1
I0
R1
R0
0
0
SCK
SI
CS
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