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參數(shù)資料
| 型號： | X9420YV |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Single Digitally Controlled (XDCP) Potentiometer |
| 中文描述： | 2.5K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO14 |
| 封裝： | PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 113K |
| 代理商： | X9420YV |
X9420
Characteristics subject to change without notice.
11 of 20
REV 1.1.6 7/30/02
www.xicor.com
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER UP REQUIREMENTS
(Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V
CC
, then V+ and V–, and then the potentiometer pins, R
H
,
R
L
, and R
W
. Voltage should not be applied to the potentiometer pins before V+ or V– is applied. The V
CC
ramp rate
specification should be met, and any glitches or slope changes in the V
CC
line should be held to <100mV if
possible. If V
CC
powers down, it should be held below 0.1V for more than 1 second before powering up again in
order for proper wiper register recall. Also, V
CC
should not reverse polarity by more than 0.5V. Recall of wiper
position will not be complete until V
CC
, V+ and V– reach their final value.
Notes:
(5) This parameter is periodically sampled and not 100% tested.
(6) t
PUR
and t
PUW
are the delays required from the time the third (last) power supply (V
CC
, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
Symbol
I
CC1
Parameter
Limits
Test Conditions
f
SCK
= 2MHz, SO = Open,
Other Inputs = V
SS
f
SCK
= 2MHz, SO = Open,
Other Inputs = V
SS
SCK = SI = V
SS
, Addr. = V
SS
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
Min.
Typ.
Max.
400
Units
μA
V
CC
Supply Current (Active)
I
CC2
V
CC
Supply Current
(Non-volatile Write)
V
CC
Current (Standby)
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
1
mA
I
SB
I
LI
I
LO
V
IH
V
IL
V
OL
1
10
10
μ
A
μ
A
μ
A
V
V
V
V
CC
x 0.7
–0.5
V
CC
+ 0.5
V
CC
x 0.1
0.4
I
OL
= 3mA
Parameter
Minimum Endurance
Data Retention
Min.
100,000
100
Units
Data Changes per Bit per Register
Years
Symbol
C
OUT
(5)
C
IN
(5)
Test
Max.
8
6
Units
pF
pF
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Output Capacitance (SO)
Input Capacitance (A0, SI, and SCK)
Symbol
t
PUR
(6)
t
PUW
(6)
t
R
V
CC
Parameter
Max.
1
5
0.2
Max.
1
5
50
Units
ms
ms
V/msec
Power-up to Initiation of Read Operation
Power-up to Initiation of Write Operation
V
CC
Power up Ramp
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