參數(shù)資料
型號(hào): X9421YV14Z
廠商: Intersil
文件頁(yè)數(shù): 17/20頁(yè)
文件大小: 0K
描述: IC XDCP SGL 64-TAP 2.5K 14-TSSOP
標(biāo)準(zhǔn)包裝: 95
系列: XDCP™
接片: 64
電阻(歐姆): 2.5k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類(lèi)型: 非易失
接口: 5 線 SPI(芯片選擇,設(shè)備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
6
FN8196.4
January 14, 2009
Write In Process
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by a
Write In Process bit (WIP). The WIP bit is read with a Read
Status command.
Instructions
Address/Identification (ID) Byte
The first byte sent to the X9421 from the host, following a CS
going HIGH to LOW, is called the Address or Identification
byte. The most significant four bits of the slave address are a
device type identifier, for the X9421 this is fixed as 0101[B]
(refer to Figure 2).
The least significant bit in the ID byte selects one of two
devices on the bus. The physical device address is defined
by the state of the A0 input pin. The X9421 compares the
serial data stream with the address input state; a successful
compare of the address bit is required for the X9421 to
successfully continue the command sequence. The A0 input
can be actively driven by a CMOS input signal or tied to VCC
or VSS.
The remaining three bits in the ID byte must be set to 110.
Instruction Byte
The next byte sent to the X9421 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next two bits point to one of four Data
Registers. The format is shown below in Figure 3.
The four high order bits of the instruction byte specify the
operation. The next two bits (R1 and R0) select one of the
four registers that is to be acted upon when a register
oriented instruction is issued. The last two bits are defined
as 0.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
VH
VL
VW
8
6
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN VW = VL
IF WCR = 3F[H] THEN VW = VH
WIPER
(WCR)
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
1
0
11
0A0
DEVICE TYPE
IDENTIFIER
DEVICE ADDRESS
1
FIGURE 2. ADDRESS/IDENTIFICATION BYTE FORMAT
I1
I2
I3
I0
R1
R0
0
REGISTER
SELECT
INSTRUCTIONS
FIGURE 3. INSTRUCTION BYTE FORMAT
X9421
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