參數(shù)資料
型號: X9428WV14-2.7T1
廠商: Intersil
文件頁數(shù): 3/21頁
文件大小: 0K
描述: IC XDCP SGL 64-TAP 10K 14-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: XDCP™
接片: 64
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
11
FN8197.1
April 26, 2006
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
S
A
C
K
wiper position
(sent by slave on SDA)
M
A
C
K
S
T
O
P
01 01 A
3
A
2 0
A
0
100 100 00
00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
S
A
C
K
wiper position
(sent by master on SDA)
S
A
C
K
S
T
O
P
01 01 A
3
A
2 0
A
0
101 000 00
00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
register
addresses
S
A
C
K
wiper position/data
(sent by slave on SDA)
M
A
C
K
S
T
O
P
0101 A
3
A
2 0
A
0
1011 R
1
R
0 00
00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
register
addresses
S
A
C
K
wiper position/data
(sent by master on SDA)
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101 A
3
A
2 0
A
0
1 100 R
1
R
0 00
00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
register
addresses
S
A
C
K
S
T
O
P
010 1 A
3
A
2 0
A
0
1101 R
1
R
0 00
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