FN8200.0 March 28, 2005 Figure 6. Three-Byte Command Sequence (Read) Figure 7. Increment/Decrement Command Sequence Increment/Decrement The fina" />
參數(shù)資料
型號(hào): X9440WV24-2.7
廠商: Intersil
文件頁數(shù): 19/21頁
文件大小: 0K
描述: IC DUAL PROG COMP 10K 24TSSOP
標(biāo)準(zhǔn)包裝: 75
系列: XDCP™
接片: 64
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 6 線 SPI(芯片選擇,設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
7
FN8200.0
March 28, 2005
Figure 6. Three-Byte Command Sequence (Read)
Figure 7. Increment/Decrement Command Sequence
Increment/Decrement
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the VL
terminal. A detailed illustration of the sequence and tim-
ing for this operation are shown in Figure 7 and 8.
Write in Process
The contents of the data registers are saved to nonvol-
atile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a write in process bit (WIP).
The WIP bit is read with a read status command.
Figure 8. Increment/Decrement Timing Limits
0
1
0
1
A1 A0
I3
I2
I1
I0
R1 R0 P1 P0
SCL
SI
CS
00
S0
0
D5 D4 D3 D2
D1 D0
Don’t Care
0
101
00
A1 A0
I3
I2
I1
I0
0
P1
P0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
SCK
SI
VW
INC/DEC CMD Issued
Voltage Out
tWRID
X9440
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