FN8201.0 April 18, 2005 CAPACITANCE Power-Up Timing and Sequence A.C. TEST CONDITIONS Note: (1) Applicable to recall and power consumption appl" />
參數(shù)資料
型號: X9448WV24I-2.7
廠商: Intersil
文件頁數(shù): 3/19頁
文件大?。?/td> 0K
描述: IC DUAL PROG COMP 10K 24TSSOP
標(biāo)準(zhǔn)包裝: 75
系列: XDCP™
接片: 64
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
11
FN8201.0
April 18, 2005
CAPACITANCE
Power-Up Timing and Sequence
A.C. TEST CONDITIONS
Note:
(1) Applicable to recall and power consumption applica-
tions
EQUIVALENT A.C. LOAD CIRCUIT
TIMING DIAGRAMS
START and STOP Timing
Input Timing
Symbol
Test
Typical
Unit
Test Conditions
CI/O
Input/output capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
CL, CH, CW
Potentiometer capacitance
10/10/25
pF
Power-up sequence(1): (1) VCC (2) V+ and V-
{V+
≤ V
CC at all times}
Power-down sequence: no limitation
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
5V
1533
100pF
SD Output
2.7V
100pF
tSU:STA
tHD:STA
tSU:STO
SCL
SDA
tR
(START)
(STOP)
tF
tR
tF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT
tBUF
X9448
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