參數(shù)資料
型號(hào)： X9448YV24
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計(jì)
英文描述： Shielded Paired Cable; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24
封裝： PLASTIC, TSSOP-24
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 127K
代理商： X9448YV24
X9448
Characteristics subject to change without notice.
4 of 20
REV 1.0 6/21/00
www.xicor.com
Voltage Comparator
The comparator compares the wiper voltage V
W
with
the external input voltage V
NI
. The comparator and its
logic level output are controlled by the Shutdown,
Latch, and Enable bits of the analog control register
(ACR). Enable connects the comparator output to the
V
OUT
pin, Latch memorizes the output logic state, and
Shutdown removes the analog section supply voltages
to save power. The analog control register is pro-
grammed using the two wire serial interface.
The ACR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the ACR. These data registers and
the ACR may be read and written by the host system.
INSTRUCTIONS AND PROGRAMMING
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9448 this
is fixed as 0101[B].
Figure 1. Address/Identification Byte Format
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9448 compares the
serial data stream with the address input state; a suc-
cessful compare of all four address bits is required for
the X9448 to respond with an acknowledge. The A
0
–
A
3
inputs can be actively driven by CMOS input sig-
nals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal nonvol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9448 initiates the internal
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9448 is
still busy with the write operation no ACK will be
returned. If the X9448 has completed the write opera-
tion an ACK will be returned and the master can then
proceed with the next operation.
Flow 1. ACK Polling Sequence
Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of two pots or one of two voltage comparators and
when applicable they point to one of four associated
registers. The format is shown below in Figure 2.
Figure 2. Instruction Byte Format
1
0
0
A3
A2
A1
A0
Device Type
Identifier
Device Address
1
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned
Further
Operation
Issue
Instruction
PROCEED
Issue STOP
NO
YES
YES
PROCEED
Issue STOP
NO
I1
I2
I3
I0
R1
R0
P1
P0
WCR and ACR Select
Register
Select
Instructions
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