參數(shù)資料
型號: X9455TV24-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Dual Two-wiper Digitally-Controlled (XDCP) Potentiometer
中文描述: DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: TSSOP-24
文件頁數(shù): 4/18頁
文件大?。?/td> 372K
代理商: X9455TV24-2.7
4
FN8202.0
November 10, 2004
V
IH
V
IL
V
OL
Input HIGH voltage
V
CC
x 0.7
-1
V
CC
+ 1
V
CC
x 0.3
0.4
V
Input LOW voltage
V
SDA pin output LOW voltage
I
OL
= 3mA
V
DC Electrical Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
Endurance and Data Retention
PARAMETER
MIN
UNITS
Minimum endurance
100,000
Data changes per bit
Data retention
100
Years
Capacitance
SYMBOL
TEST
TEST CONDITIONS
MAX
UNITS
C
IN/OUT
(Note 5) Input / Output capacitance (SDA)
V
OUT
= 0V
8
pF
C
IN
(Note 5)
Input capacitance (DS0, DS1, CS, U/D,
SCL, WP, A2, A1
and A0
)
V
IN
= 0V
6
pF
Power-Up Timing
SYMBOL
PARAMETER
MAX
UNITS
t
D
(Notes 5, 9)
Power Up Delay from V
CC
power up (V
CC
above 2.7V) to wiper position recall
completed, and communication interfaces ready for operation.
2
ms
A.C. Test Conditions
Input Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing threshold level
V
CC
x 0.5
External load at pin SDA
2.3k
to V
CC
and 100 pF to V
SS
2-Wire Interface Timing (s)
SYMBOL
PARAMETER
MIN
MAX
UNITS
f
SCL
Clock Frequency
400
kHz
t
HIGH
Clock High Time
600
ns
t
LOW
Clock Low Time
1300
ns
t
SU:STA
Start Condition Setup Time
600
ns
t
HD:STA
Start Condition Hold Time
600
ns
t
SU:STO
Stop Condition Setup Time
600
ns
t
SU:DAT
SDA Data Input Setup Time
100
ns
t
HD:DAT
SDA Data Input Hold Time
30
ns
t
R
(Note 5)
SCL and SDA Rise Time
300
ns
t
F
(Note 5)
SCL and SDA Fall Time
300
ns
t
AA
(Note 5)
SCL Low to SDA Data Output Valid Time
0.9
μs
t
DH
SDA Data Output Hold Time
0
ns
t
IN
(Note 5)
Pulse Width Suppression Time at SCL and SDA inputs
50
ns
t
BUF
(Note 5)
Bus Free Time (Prior to Any Transmission)
1200
ns
X9455
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