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參數(shù)資料
| 型號： | X9455YV24-2.7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/19頁 |
| 文件大小： | 0K |
| 描述： | IC DCP DUAL 2K 256TAP 24-TSSOP |
| 標準包裝： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 2.8k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 9 線串行（芯片選擇，設備位址，動觸點位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | X9455ZV24-2.7 X9455ZV24-2.7-ND |
15
FN8202.1
July 28, 2006
Page Write Operation
As stated previously, the memory is organized as a single
Status Register (SR), and four pages of four registers each.
Each page contains one Data Register for each wiper.
Normally a page write operation will be used to efficiently
update all four Data Registers and WCR in a single Write
command. Note the special sequence for writing to a page:
First wiper 0A, then 1B, then 1A, then 0B as shown in Figure
In order to perform a Page Write operation to the memory
array, the NVEnable bit in the SR must first be set to “1”.
A Page Write operation is initiated in the same manner as
the Byte Write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 4 bytes (See Figure 9). After the receipt of
each byte, the X9455 responds with an ACK, and the
internal WCR address is incremented by one. The page
address remains constant. When the address reaches the
end of the page, it “rolls over” and goes back to the first byte
of the same page.
For example, if the master writes three bytes to a page
starting at location DR1A2, the first two bytes are written to
locations DR1A2 and DR0B2, while the last byte is written to
location DR0A2. Afterwards, the WCR address would point
to location DR1B2. If the master supplies more than four
bytes of data, then new data overwrites the previous data,
one byte at a time.
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle. If the WP pin is low,
the nonvolatile write cycle doesn’t start and the bytes are
discarded.
Notice that the Data Bytes are also written to the WCR of the
corresponding WCRs, therefore in the above example,
WCR1A, WCR0B, and WCR0A are also written, and
WCR1B is updated with the contents of DR1B2.
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Data
Byte
A
C
K
Signals from the
Master
Signals from the
Slave
A
C
K
0
11
A
C
K
Write
Signal at SDA
FIGURE 7. BYTE WRITE SEQUENCE
WCR
WCR0A
→ WCR1B → WCR1A → WCR0B
DR Level 0
DR0A0
→ DR1B0 → DR1A0 → DR0B0
DR Level 1
DR0A1
→ DR1B1 → DR1A1 → DR0B1
DR Level 2
DR0A2
→ DR1B2 → DR1A2 → DR0B2
DR Level 3
DR0A3
→ DR1B3 → DR1A3 → DR0B3
FIGURE 8. PAGE WRITE SEQUENCE*
*Page writes may wrap around to the first address on a page from
the last address.
2 < n < 4
Signals from the
Master
Signals from the
Slave
Signal at SDA
S
t
a
r
t
Slave
Address
Byte
A
C
K
A
C
K
0
11
Data Byte (1)
S
t
o
p
A
C
K
A
C
K
Data Byte (n)
Write
FIGURE 9. PAGE WRITE OPERATION
X9455
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