參數(shù)資料
型號(hào): X9455YV24I-2.7
廠商: INTERSIL CORP
元件分類(lèi): 數(shù)字電位計(jì)
英文描述: Dual Two-wiper Digitally-Controlled (XDCP) Potentiometer
中文描述: DUAL 2.8K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: 4.40 MM, TSSOP-24
文件頁(yè)數(shù): 8/18頁(yè)
文件大?。?/td> 372K
代理商: X9455YV24I-2.7
8
FN8202.0
November 10, 2004
Principles of Operation
The X9455 is an integrated circuit incorporating two resistor
arrays with dual wipers on each array, their associated
registers and counters, and the serial interface logic
providing direct communication between the host and the
digitally controlled potentiometers. This section provides
detail description of the following:
Resistor Array
Up/Down Interface
2-wire Interface
Resistor Array Description
The X9455 is comprised of two resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R
Hi
and
R
Li
inputs). (See Figure 1.)
Each array has two independent wipers. At both ends of
each array and between each resistor segment are two
switches, one connected to each of the wiper pins (R
WiA
and
R
WiB
).
Within each individual array only one switch of each wiper
may be turned on at a time.
These switches are controlled by two Wiper Counter
Register (WCR). The 8-bits of the WCR are decoded to
select and enable one of 256 switches. Note that each wiper
has a dedicated WCR. When all bits of a WCR are zeroes,
the switch closest to the corresponding R
L
pin is selected.
When all bits of a WCR are ones, the switch closest to the
corresponding R
H
pin is selected.
The WCRs are volatile and may be written directly. There
are four non-volatile Data Registers (DR) associated with
each WCR. Each DR can be loaded into WCR. All DRs and
WCRs can be read or written.
Power Up and Down Requirements
During power up CS must be high to avoid inadvertant
“store” operations. At power up, the contents of Data
Registers Level 0 (DR0A0, DR0B0, DR1A0, and DR1B0),
are loaded into the corresponding wiper counter register.
One of
256
Decoder
WCRiA[7:0]
= FF hex
R
Hi
R
WiA
R
Li
255
254
255
254
Volatile
8-bit
Wiper
Counter
Register
WCRiA
Four
Non-Volatile
Data
Registers
DRiA0, DRiA1,
DRiA2, and
DRiA3
“i” is either 0 or 1
WCRiB[7:0]
= 00 hex
1
0
R
WiB
0
1
WCRiB[7:0]
= FF hex
WCRiA[7:0]
= 00 hex
Volatile
8-bit
Wiper
Counter
Register
WCRiB
Four
Non-Volatile
Data
Registers
DRiB0, DRiB1,
DRiB2, and
DRiB3
2-wire and
Up/Down Interfaces
.
.
.
.
.
.
FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP
X9455
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