參數(shù)資料
型號(hào)： X9470V24I
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： RF Power Amplifier (PA) Bias Controller
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO24
封裝： PLASTIC, TSSOP-24
文件頁(yè)數(shù)： 9/25頁(yè)
文件大?。?/td> 542K
代理商： X9470V24I
PeimnayInomaion
9 of 25
REV 11.16 3/20/03
www.xicor.com
Preliminary Information
X9470
Write Cycle Timing
Power Up Timing
Note:
Delays are measured from the time V
CC
is stable until the specified operation can be initiated. These parameters are not 100% tested.
Proper recall of stored wiper setting requires a V
CC
power-up ramp that is monotonic and with noise or glitches < 100mV. It is important
to correctly sequence voltages in an LDMOS amplifier circuit. For the X9470 typical application, the V
CC
, then V+ pins should be pow-
ered before the V
DD
of the LDMOS to prevent LDMOS damage. Under no circumstances should the V
DD
be applied to the LDMOS
device before V
CC
and V+ are applied to the X9470.
DCP Default Power-up Tap Positions (shipped from factory)
Nonvolatile Write Cycle Timing
Note:
t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Symbol
t
r
V
CC
(10)
Parameter
Min.
0.2
Max.
50
Unit
V/ms
V
CC
Power-up rate
VREF DCP
Bias Adjust DCP
0
0
Symbol
t
WC
(10)
Parameter
Write Cycle Time
Min.
Typ.
(1)
5
Max.
10
Unit
ms
SCL
SDA
t
WC
8th Bit of Last Byte
ACK
Stop
Condition
Start
Condition
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