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參數(shù)資料
| 型號： | X9521 |
| 英文描述： | Dual DCP, EEPROM Memory |
| 中文描述： | 雙二氯酚，EEPROM存儲器 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 434K |
| 代理商： | X9521 |
REV 1.1.9 1/30/03
Characteristics subject to change without notice.
14 of 26
www.xicor.com
X9521
– Preliminary Information
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset the
BL0 and BL0 bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin
of the X9521 is active (HIGH) (See "WP: Write Protection
Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 19).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each regis-
ter read operation. The X9521 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write opera-
tion.
When reading the contents of the CONSTAT register, the
bits CS7-CS5 and CS0 will always return “0”.
DATA PROTECTION
There are a number of levels of data protection features
designed into the X9521. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires the
setting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain regions
of the EEPROM memory, as well as to all the DCPs. One
further level of data protection in the X9521, is incorpo-
rated in the form of the Write Protection pin.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9521.
The table below (X9521 Write Permission Status) sum-
marizes the effect of the WP pin (and Block Lock), on the
write permission status of the device.
Additional Data Protection Features
In addition to the preceding features, the X9521 also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
0
Slave
Address
Address
Byte
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 19. CONSTAT Register Read Command Sequence
0 1 0 0 1 0
1
1
0 1 0 0 1 0
WRITE Operation
“Dummy” Write
READ Operation
CS7
…
CS0
X9521 Write Permission Status
Block Lock
Bits
WP
DCP Volatile Write
Permitted
DCP Nonvolatile
Write Permitted
Write to EEPROM
Permitted
Write to CONSTAT Register
Permitted
BL0
BL1
Volatile Bits
Nonvolatile
Bits
x
1
1
NO
NO
NO
NO
NO
1
x
1
NO
NO
NO
NO
NO
0
0
1
YES
NO
NO
NO
NO
x
1
0
0
0
NO
NO
Not in locked region
YES
YES
1
x
NO
NO
Not in locked region
YES
YES
0
0
YES
YES
Yes (All Array)
YES
YES
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9521_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual DCP, EEPROM Memory |
| X9521V20I | 功能描述:IC LASR CTRLR 2CHAN 5.5V 20TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 激光驅(qū)動器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:激光二極管驅(qū)動器 數(shù)據(jù)速率:- 通道數(shù):4 電源電壓:3.3V 電流 - 電源:- 電流 - 調(diào)制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
| X9521V20I-A | 功能描述:IC DCP DUAL EEPROM MEM 20-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 激光驅(qū)動器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:激光二極管驅(qū)動器 數(shù)據(jù)速率:- 通道數(shù):4 電源電壓:3.3V 電流 - 電源:- 電流 - 調(diào)制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
| X9521V20I-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual DCP, EEPROM Memory |
| X9521V20IZ-A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual DCP, EEPROM Memory |
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