參數(shù)資料
型號: X9522B20I-B
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Laser Diode Control for Fiber Optic Modules
中文描述: DIGITAL POTENTIOMETER, PBGA20
封裝: BGA-20
文件頁數(shù): 3/29頁
文件大小: 486K
代理商: X9522B20I-B
3
FN8208.0
March 10, 2005
PIN ASSIGNMENT
Pin
XBGA
Name
R
H2
R
w2
R
L2
Function
1
B3
Connection to end of resistor array for (the 256 Tap) DCP 2.
2
A3
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
3
A4
Connection to other end of resistor array for (the 256 Tap) DCP 2.
4
B4
V3
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When
the V3 input is higher than the
V
TRIP3
threshold voltage, V3RO makes a transition to a HIGH
level. Connect V3 to V
SS
when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is
greater than
V
TRIP3
and goes LOW when V3 is less than V
TRIP3
. There is no delay circuitry
on this pin. The V3RO pin requires the use of an external “pull-up” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Pro-
tection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Al-
so, when the Write Protection is enabled, and the DCP Write Lock feature is active (i.e. the
DCP Write Lock bit is set to “1”), then no “write” (volatile or nonvolatile) operations can be per-
formed in the device (including the wiper position of any of the integrated Digitally Controlled
Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating
the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for
data input and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires an
external pull up resistor.
Ground.
5
C3
V3RO
7
C4
WP
8
D4
SCL
9
E4
SDA
10
E1
Vss
R
L1
R
w1
R
H1
R
H0
R
W0
R
L0
11
E3
Connection to other end of resistor for (the 100 Tap) DCP 1.
12
E2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
13
D1
Connection to end of resistor array for (the 100 Tap) DCP 1.
14
D2
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
15
C1
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
16
C2
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
17
B1
V2
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When
the V2 input is greater than the
V
TRIP2
threshold voltage, V2RO makes a transition to a HIGH
level. Connect V2 to V
SS
when not used.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is great-
er than
V
TRIP2
, and goes LOW when V2 is less than
V
TRIP2
. There is no power-up reset delay
circuitry on this pin. The V2RO pin requires the use of an external “pull-up” resistor.
Supply Voltage.
No Connect.
18
A1
V2RO
20
6, 19
A2
Vcc / V1
NC
B2, D3
X9522
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X9522V20IZ-A 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple DCP, Dual Voltage Monitors