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參數(shù)資料
| 型號(hào)： | X95840 |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Quad Digital Controlled Potentiometers (XDCP)(四數(shù)控電位器（XDCP）) |
| 中文描述： | 四數(shù)字（數(shù)字電位器）（四數(shù)控電位器（數(shù)字電位器）控制電位器） |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | X95840 |
X95840
4 of 12
REV 1.16 7/28/04
www.xicor.com
OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Symbol
Parameter
supply current
(Volatile write/read)
V
CC
supply current
(nonvolatile write)
V
CC
current
(standby)
Leakage current, at
pins A0, A1, A2, SDA,
SCL, and WP pins
DCP wiper reponse time
Limits
1
Test Conditions
Min.
Typ.
Max.
1
Units
mA
I
CC1
V
CC
f
Active, Read and Volatile Write States only)
f
SCL
= 400kHz; SDA = Open; (for 2-Wire,
Active, Nonvolatile Write State only)
V
CC
= +5.5V, 2 Wire Interface in Standby State
V
CC
= +3.6V, 2 Wire Interface in Standby State
Voltage at pin from GND to V
SCL
= 400kHz;SDA = Open; (for 2-Wire,
I
CC2
3
mA
I
SB
5
2
10
μA
μA
μA
I
LkgDig
-10
CC
t
DCP
(15)
1
μs
SCL falling edge of last bit of DCP Data Byte to wiper
change
Minimum V
CC
at which memory recall occurs
Vpor
VccRamp
t
D
(15)
Power-on recall voltage
V
CC
ramp rate
Power up delay
1.8
0.2
2.6
V
V/ms
ms
3
V
CC
above Vpor, to DCP Initial Value Register recall
completed, and 2-Wire Interface in standby state
EEPROM Specs
EEPROM Endurance
EEPROM Retention
150,000
50
Cycles
Years
Temperature
≤
75°C
Serial Interface Specs
V
IL
WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage
WP, A2, A1, A0, SDA, and
SCL input buffer HIGH
voltage
SDA and SCL input buffer
hysterisis
SDA output buffer LOW
voltage, sinking 4 mA
WP, A2, A1, A0, SDA, and
SCL pin capacitance
SCL frequency
Pulse width suppression
time at SDA and SCL
inputs
SCL falling edge to SDA
output data valid
Time the bus must be free
before the start of a new
transmission
Clock LOW time
Clock HIGH time
START condition setup
time
START condition hold
time
Input data setup time
-0.3
0.3*Vcc
V
V
IH
0.7*Vcc
Vcc+0.3
V
Hysterisis
(15)
0.05*
Vcc
0
V
V
OL
(15)
0.4
V
Cpin
(15)
10
pF‘
f
SCL
t
IN
(15)
400
50
kHz
ns
Any pulse narrower than the max spec is suppressed.
t
AA
(15)
900
ns
SCL falling edge crossing 30% of V
CC
, until SDA ex-
its the 30% to 70% of V
CC
window.
SDA crossing 70% of V
CC
during a STOP condition,
to SDA crossing 70% of V
CC
during the following
START condition.
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both crossing
70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to SCL
falling edge crossing 70% of V
CC
.
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
t
BUF
(15)
1300
ns
t
LOW
t
HIGH
t
SU:STA
1300
600
600
ns
ns
ns
t
HD:STA
600
ns
t
SU:DAT
100
ns
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