參數(shù)資料
型號： X95840WV20IZ-2.7
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計
英文描述： Quad Digital Controlled Potentiometers
中文描述： QUAD 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO20
封裝： ROHS COMPLIANT, PLASTIC, TSSOP-20
文件頁數(shù)： 5/13頁
文件大小： 1145K
代理商： X95840WV20IZ-2.7
5
FN8213.1
September 27, 2005
SDA vs SCL Timing
t
SU:DAT
Input data setup time
From SDA exiting the 30% to 70% of V
CC
window, to
SCL rising edge crossing 30% of V
CC
100
ns
t
HD:DAT
Input data hold time
From SCL rising edge crossing 70% of V
CC
to SDA
entering the 30% to 70% of V
CC
window.
0
ns
t
SU:STO
STOP condition setup time
From SCL rising edge crossing 70% of V
CC
, to SDA
rising edge crossing 30% of V
CC
.
600
ns
t
HD:STO
STOP condition setup time
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
600
ns
t
DH
(Note 15)
Output data hold time
From SCL falling edge crossing 30% of V
CC
, until SDA
enters the 30% to 70% of V
CC
window.
0
ns
t
R
(Note 15)
SDA and SCL rise time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
t
F
(Note 15)
SDA and SCL fall time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb
(Note 15)
Capacitive loading of SDA or
SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 15) SDA and SCL bus pull-up
resistor off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
1
k
t
WP
(Notes 15, 16)
Non-volatile Write cycle time
12
20
ms
t
SU:WPA
A2, A1, A0, and WP setup
time
Before START condition
600
ns
t
HD:WPA
A2, A1, A0, and WP hold
time
After STOP condition
600
ns
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(Input Timing)
SDA
(Output Timing)
t
F
t
LOW
t
BUF
t
AA
t
R
X95840
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