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參數(shù)資料
| 型號： | X95840WV20IZ-2.7T1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL QUAD 10K OHM 20TSSOP |
| 標準包裝： | 1 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 ±45 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1237 (CN2011-ZH PDF) |
| 其它名稱： | X95840WV20IZ-2.7T1DKR |
4
FN8213.2
July 5, 2006
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
ICC1
VCC Supply Current
(Volatile write/read)
fSCL = 400kHz; SDA = Open; (for I
2C,
Active, Read and Volatile Write States only)
1mA
ICC2
VCC Supply Current
(nonvolatile write)
fSCL = 400kHz; SDA = Open; (for I
2C,
Active, Nonvolatile Write State only)
3mA
ISB
VCC Current (standby)
VCC = +5.5V, I
2C Interface in Standby State
5
A
VCC = +3.6V, I
2C Interface in Standby State
2
A
ILkgDig
Leakage Current, at
Pins A0, A1, A2, SDA, SCL,
and WP Pins
Voltage at pin from GND to VCC
-10
10
A
tDCP
(Note 15)
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to wiper
change
1s
Vpor
Power-on Recall Voltage
Minimum VCC at which memory recall occurs
1.8
2.6
V
VccRamp
VCC Ramp Rate
0.2
V/ms
Power-up Delay
VCC above Vpor, to DCP Initial Value Register recall
completed, and
I2C Interface in standby state
3ms
EEPROM SPECS
EEPROM Endurance
150,000
Cycles
EEPROM Retention
Temperature
≤ 75°C
50
Years
SERIAL INTERFACE SPECS
VIL
WP, A2, A1, A0, SDA, and
SCL Input Buffer LOW
Voltage
-0.3
0.3*VCC
V
VIH
WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage
0.7*VCC
VCC+0.3
V
Hysteresis
(Note 15)
SDA and SCL Input Buffer
Hysteresis
0.05*
VCC
V
Voltage, Sinking 4mA
00.4
V
Cpin
(Note 15)
WP, A2, A1, A0, SDA, and
SCL Pin Capacitance
10
pF
fSCL
SCL frEquency
400
kHz
Time at SDA and SCL Inputs
Any pulse narrower than the max spec is suppressed.
50
ns
Output Data Valid
SCL falling edge crossing 30% of VCC, until SDA exits
the 30% to 70% of VCC window.
900
ns
tBUF
(Note 15)
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of VCC during a STOP condition, to
SDA crossing 70% of VCC during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup
Time
SCL rising edge to SDA falling edge. Both crossing
70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to SCL
falling edge crossing 70% of VCC.
600
ns
X95840
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