參數(shù)資料
型號(hào): X96011V14IZ
廠商: INTERSIL CORP
元件分類: 溫度/濕度傳感器
英文描述: Temperature Sensor with Look Up Table Memory and DAC
中文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2Cel, RECTANGULAR, SURFACE MOUNT
封裝: ROHS COMPLIANT, PLASTIC, TSSOP-14
文件頁數(shù): 5/23頁
文件大?。?/td> 335K
代理商: X96011V14IZ
5
FN8215.1
October 25, 2005
D/A CONVERTER CHARACTERISTICS
(See pg. 5 for standard conditions)
Notes: 1. LSB is defined as
divided by the resistance between R1 or R2 to Vss.
2. Offset
DAC
: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSError
DAC
: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The Offset
DAC
is subtracted from the measured value before calculating FSError
DAC
.
DNL
DAC
: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNL
DAC
.
INL
DAC
: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
3.
These parameters are periodically sampled and not 100% tested.
Symbol
IFS
Offset
DAC
FSError
DAC
DNL
DAC
Parameter
Min
1.56
1
-2
-0.5
Typ
1.58
Max
1.6
1
2
0.5
Unit
mA
LSB
LSB
LSB
Test Conditions / Notes
DAC input Byte = FFh,
Source or sink mode, V(Iout) is
Vcc–1.2V in source mode and
1.2V in sink mode.
See notes 1 and 2.
Iout full scale current
Iout D/A converter offset error
Iout D/A converter full scale error
Iout D/A converter
Differential Nonlinearity
Iout D/A converter Integral
Nonlinearity with respect to a
straight line through 0 and the full
scale value
I1 Sink Voltage Compliance
INL
DAC
-1
1
LSB
VISink
1.2
Vcc
V
In this range the current at I1
vary < 1%
In this range the current at I1
vary < 1%
DAC input byte changing from
00h to FFh and vice
versa, V(I1) is Vcc - 1.2V in
source mode and 1.2V in sink
mode.
See note 3.
VISource
I1 Source Voltage Compliance
0
Vcc -
1.2
0
V
I
OVER
I1 overshoot on D/A Converter data
byte transition
I1 undershoot on D/A Converter
data byte transition
I1 rise time on D/A Converter data
byte transition; 10% to 90%
Temperature coefficient of output
current Iout
2
3
255
[
μ
A
I
UNDER
0
μ
A
t
rDAC
5
30
μ
s
TCO
I1I2
±200
ppm/°C
See Figure 5.
V(VRef)
x
]
X96011
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