參數(shù)資料
型號(hào)： x96012
英文描述： Universal Sensor Conditioner with Dual Look Up Table Memory and DACs(帶雙查尋表存儲(chǔ)器和數(shù)模轉(zhuǎn)換器的通用傳感器控制器)
中文描述： 通用傳感器護(hù)發(fā)高達(dá)Table內(nèi)存和DAC雙查詢（帶雙查尋表存儲(chǔ)器和數(shù)模轉(zhuǎn)換器的通用傳感器控制器）
文件頁數(shù)： 6/27頁
文件大?。?/td> 526K
代理商： X96012
6 of 27
REV 1.7 6/23/03
www.xicor.com
X96012
D/A CONVERTER CHARACTERISTICS
(See pg. 4 for Standard Conditions)
Notes:
1.
DAC input Byte = FFh, Source or sink mode.
3
2. LSB is defined as 2
255
3. Offset
expressed in LSB.
FSError
FFh. It is expressed in LSB. The Offset
DNL
DAC
: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Off-
set and Full Scale Error before calculating DNL
DAC
.
INL
DAC
: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after
adjusting the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
DAC
: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
DAC
: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is
is subtracted from the measured value before calculating FSError
DAC
DAC
.
4.
These parameters are periodically sampled and not 100% tested.
5.
V(I1) and V(I2) are V
CC
–1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%.
6.
The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V
voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.
CC
= 4.5V. The compliance
Symbol
IFS
00
Parameter
Min
1.56
Typ
1.58
Max
1.6
3.2
0.5
Unit
mA
mA
mA
Test Conditions / Notes
See note 1, 5
See note 1, 4, 6
DAC input Byte = FFh,
Source or sink mode, V(I1)
and V(I2) are Vcc–1.2V in
source mode and 1.2V in sink
mode.
See notes 2 and 3.
I1 or I2 full scale current, with external
resistor setting
IFS
01
I1 or I2 full scale current, with internal
low current setting option
I1 or I2 full scale current, with internal
middle current setting option
I1 or I2 full scale current, with internal
high current setting option
I1 or I2 D/A converter offset error
I1 or I2 D/A converter full scale error
I1 or I2 D/A converter
Differential Nonlinearity
I1 or I2 D/A converter Integral Nonlin-
earity with respect to a straight line
through 0 and the full scale value
I1 or I2 Sink Voltage Compliance
0.3
0.4
IFS
10
0.64
0.85
1.06
mA
IFS
11
1
1.3
1.6
mA
Offset
FSError
DNL
DAC
1
-2
-0.5
1
2
LSB
LSB
LSB
DAC
DAC
0.5
INL
DAC
-1
1
LSB
V
ISink
1.2
2.5
0
0
Vcc
Vcc
V
V
V
V
μ
See note 5
See note 4, 6
See note 5
See note 4, 6
DAC input byte changing
from 00h to FFh and vice
versa, V(I1) and V(I2) are
Vcc–1.2V in source mode
and 1.2V in sink mode.
See note 4.
V
ISource
I1 or I2 Source Voltage Compliance
Vcc-1.2
Vcc-2.5
0
I
OVER
I1 or I2 overshoot on D/A Converter
data byte transition
I1 or I2 undershoot on D/A Converter
data byte transition
I1 or I2 rise time on D/A Converter data
byte transition; 10% to 90%
Temperataure coefficient of output
current I1 or I2 when using internal
resistor setting
A
I
UNDER
0
μ
A
t
rDAC
5
30
μ
s
TCO
I1I2
±200
ppm/
°C
See Figure 8.
Bits I1FSO[1:0]
Bits I2FSO[1:0]
VRMbit = “1”
≠
≠
00
002,
2
or
V(VRef)
x
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參數(shù)描述
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