參數(shù)資料
型號(hào)： X96012
廠商： Intersil Corporation
英文描述： Universal Sensor Conditioner with Dual Look-up Table Memory and DACs(通用傳感器調(diào)節(jié)器，帶雙查找表存儲(chǔ)器及DACs)
中文描述： 通用傳感器護(hù)發(fā)雙查找表內(nèi)存和DAC（通用傳感器調(diào)節(jié)器，帶雙查找表存儲(chǔ)器及數(shù)模轉(zhuǎn)換器-）
文件頁(yè)數(shù)： 19/23頁(yè)
文件大?。?/td> 353K
代理商： X96012
19
FN8216.3
February 20, 2008
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte. Refer to Figure 16. This byte includes
three parts:
The four MSBs (SA7 - SA4) are the Device Type
Identifier, which must always be set to 1010 in order to
select the X96012.
The next three bits (SA3 - SA1) are the Device Address bits
(AS2 - AS0). To access any part of the X96012’s memory,
the value of bits AS2, AS1, and AS0 must correspond to the
logic levels at pins A2, A1, and A0 respectively.
The LSB (SA0) is the R/W bit. This bit defines the operation
to be performed on the device being addressed. When the
R/W bit is “1”, then a Read operation is selected. A “0”
selects a Write operation (refer to Figure 16).
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly
issued (including the final STOP condition), the X96012
initiates an internal high voltage write cycle. This cycle
typically requires 5ms. During this time, any Read or Write
command is ignored by the X96012. Write Acknowledge
Polling is used to determine whether a high voltage write
cycle is completed.
During acknowledge polling, the master first issues a START
condition followed by a Slave Address Byte. The Slave
Address Byte contains the X96012’s Device Type Identifier
and Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is busy
within the high voltage cycle, then no ACK is returned. If the
high voltage cycle is completed, an ACK is returned and the
master can then proceed with a new Read or Write
operation. Refer to Figure 17.
Byte Write Operation
In order to perform a Byte Write operation to the memory
array, the Write Enable Latch (WEL) bit of the Control 6
Register must first be set to “1”. See “WEL: Write Enable
Latch (Volatile)” on page 12.
For any Byte Write operation, the X96012 requires the Slave
Address Byte, an Address Byte, and a Data Byte. See
Figure 18. After each of them, the X96012 responds with an
ACK. The master then terminates the transfer by generating a
STOP condition. At this time, if all data bits are volatile, the
X96012 is ready for the next read or write operation. If some
bits are nonvolatile, the X96012 begins the internal write cycle
to the nonvolatile memory. During the internal nonvolatile write
cycle, the X96012 does not respond to any requests from the
master. The SDA output is at high impedance.
A Byte Write operation can access bytes at locations 00h
through FEh directly, when setting the Address Byte to 00h
through FEh respectively. Setting the Address Byte to FFh
accesses the byte at location 100h. The other sixteen bytes,
at locations FFh and 101h through 10Fh can only be
accessed using Page Write operations. The byte at location
FFh can only be written using a “Page Write” operation.
Writing to Control bytes which are located at byte addresses
80h through 8Fh is a special case described in “Writing to
Control Registers” on page 20.
Page Write Operation
The 2176-bit memory array is physically realized as one
contiguous array, organized as 17 pages of 16 bytes each. A
“Page Write” operation can be performed to any of the GPM
or LUT pages. In order to perform a Page Write operation to
the memory array, the Write Enable Latch (WEL) bit in
Control register 6 must first be set See “WEL: Write Enable
Latch (Volatile)” on page 12.
A Page Write operation is initiated in the same manner as
the byte write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 16 bytes (see Figure 19). After the receipt of
each byte, the X96012 responds with an ACK, and the
internal byte address counter is incremented by one. The
page address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to the first
byte of the same page.
ACK RETURNED
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
BYTE LOAD COMPLETED BY ISSUING
STOP. ENTER ACK POLLING
ISSUE STOP
ISSUE START
NO
YES
NO
CONTINUE NORMAL READ OR
WRITE COMMAND SEQUENCE
PROCEED
YES
COMPLETE. CONTINUE COMMAND
SEQUENCE.
HIGH VOLTAGE
ISSUE STOP
FIGURE 17. ACKNOWLEDGE POLLING SEQUENCE
X96012
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
X96012_08 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Universal Sensor Conditioner with Dual Look-up Table Memory and DACs
X96012V14I 功能描述:IC CNTRLR UNIV MEM/DAC 14-TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
X96012V14IZ 功能描述:板上安裝溫度傳感器 UNIVERSAL SENSOR CONDITIO W/DL LOOKUP RoHS:否 制造商:Omron Electronics 輸出類型:Digital 配置: 準(zhǔn)確性:+/- 1.5 C, +/- 3 C 溫度閾值: 數(shù)字輸出 - 總線接口:2-Wire, I2C, SMBus 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 50 C 最小工作溫度:0 C 關(guān)閉: 安裝風(fēng)格: 封裝 / 箱體: 設(shè)備功能:Temperature and Humidity Sensor
X96012V14IZT1 功能描述:板上安裝溫度傳感器 UNIVERSAL SENSOR CONDITIO W/DL LOOKUP RoHS:否 制造商:Omron Electronics 輸出類型:Digital 配置: 準(zhǔn)確性:+/- 1.5 C, +/- 3 C 溫度閾值: 數(shù)字輸出 - 總線接口:2-Wire, I2C, SMBus 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 50 C 最小工作溫度:0 C 關(guān)閉: 安裝風(fēng)格: 封裝 / 箱體: 設(shè)備功能:Temperature and Humidity Sensor
X9601XEVAL 制造商:Intersil Corporation 功能描述:X9601 EVALUATION BOARD - Bulk
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