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參數(shù)資料
| 型號(hào)： | X9C503 |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | EEPOT Nonvolatile Digital Potentiometer(100個(gè)抽頭,-5V~+5V,50K總電阻,非易失性數(shù)字電位器) |
| 中文描述： | EEPOT非易失數(shù)字電位器（100個(gè)抽頭，- 5V的?5V的，50K的總電阻，非易失性數(shù)字電位器） |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 87K |
| 代理商： | X9C503 |
Xicor Application Note
AN120-5
AN120
The circuit consists of op amp IC1 (for example, Linear
Technology’s LT1226), CMOS multiplexer S
an HC4053), and digital potentiometer P1 (Xicor’s
X9C103). The topology supports two modes of operation,
as selected by the TTL/CMOS-compatible NADJ signal.
NADJ=0 connects IC1
as a standard noninverting gain
block. The circuit values shown, combined with the
impressive specs of the frequency-compensated LT1226,
provide a gain of 1001 with bandwidth extending from DC
to beyond 500 kHz and input-related noise of
approximately 2 nV/
Hz.
C
(one-third of
Null-adjustment mode occurs when NADJ=1 disconnects
the input source and effectively causes IC1’s output to run
open-loop. IC1’s output and then slews to one rail or the
other, as determined by the sign of its net offset error. If
R3=RS–R1||R2, where RS is the DC source resistance,
then IC1’s output reflects the sum of both voltage
current bias errors. The circuit level-shifts and filters IC1’s
output and applies it to the up/down control input of P1.
This action sets up P
1
’s internal up/down-counter logic to
increment of decrement one step, depending on the state of
IC1’s output and thus on the sign of IC1’s offset. The
counter step occurs on the subsequent NADJ=0 transition.
and
The connection of the VL, VW, and VH terminals of P1 to
the nulling terminals of IC1 closes a feedback loop that
tends to push IC1 one step toward null for every 10 cycles
of NADJ. Because the X9C103 has 100 resolved settings,
the technique requires a maximum of 99 NADJ pulses to
complete the nulling process. After nulling, P1 retains the
final null setting in digital memory as long as the 5V supply
remains connected or until the nulling process repeats.
Observed performance reveals that using an OP37
consistently achieves residual-offset errors of less than 5 μV.
If it is inconvenient to provide an external NADJ clock
source in a given application, you can add the SA/SB
multivibrator at Node 1. This 1-kHz clock circuit receives
its gating from the CMOS-compatible anull signal, such
that anull=1 enables continuous null adjustment, and
anull=0 enables normal amplifier operation. The maximum
anull duration required to achieve initial null is 100msec. If
desired, you can also include D1, R8, and C3 at Node 2 to
provide an automatic null on each power-up cycle.
Although Figure 4 shows an LT1226, the circuit works
without modification with an OP37 and LT1028. The circuit
is also pin-compatible with the popular LT1128, OP07,
OP77, OP177, and μ725 op amps. With these op amps,
however, the circuit may require a slower NADJ clock rate
and a longer nulling interval (increase C2 and C3),
because of the lower gain-bandwidth product of these
compensated types. The circuit can accommodate many
other op-amp types with a simple change of pin
connections. The circuit can handle 15V positive-rail
operations by substituting an X9312 for the X9C103 with
no other changes.
Power Amplifier Biasing
The day may be near when every amplifier application can
be served simply by finding the right off-the-shelf stand-
alone chip. Maybe. But for now, many jobs require that
even the best monolithic devices be supplemented with a
sprinkling of active discrete devices. One such category of
application is the high-output-current, high-frequency
buffer amplifier in Figure 5.
Of course it’s simplicity in itself to add an arbitrary amount
of muscle to a “milquetoast” op amp by following it with a
class AB complementary bipolar emitter-follower or FET
source follower pair like Q1 and Q2 in the Figure 5. Many
successful driver designs are based on just this
elementary topology. But all such designs must confront
the problem of stable DC biasing of the follower while
avoiding unconscionable amounts of quiescent power
draw and unbearable levels of harmonic distortion. This is
a problem fraught with the classic twin-design-bogeymen
of thermal runaway and cross-over distortion.
The new solution to this old puzzle described here
comprises an automatic bias adjustment loop consisting
of a Xicor digital potentiometer P1, International Rectifier
photovoltaic optoisolator O1, CMOS switches S1-S3, and
Linear Technology op amps A2-3. The resulting
adjustment loop includes two modes of operation selected
by the CMOS/TTL-compatible ADJ input.
When ADJ=0, S3 closes a normal feedback loop around
A1 and the Q1/Q2 pair thus forcing the circuit to become a
fairly normal, gain of -5 amplifier with a bandpass of DC to
10 MHz, full power bandwidth (limited by A1 slew) of 5
MHz, and output limits of ±10V and ±10A. Harmonic
distortion over the full operating range is minimized by the
impressive GBW of capacitive-load-compatible A1
combined with stable quiescent biasing of the Q1/Q2 pair
to a thrifty no signal value of 50 mA. The trick behind these
performance numbers is the way an appropriate bias level
for the follower is achieved, one that’s independent of
temperature and component tolerance variations.
To understand how this is done, consider how the circuit
rearranges itself when ADJ=1 causes S3 to disconnect
A1’s input from the signal source and substitute a ground
reference. Simultaneously, the S1/S2, 20-Hz multivibrator
is enabled and begins clocking P1. In response, P1 begins
to vary the input to A3, which then servos the control
current into O1 and thus the net gate bias voltage at the
follower MOSFETs.
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參數(shù)描述 |
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| X9C503DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Potentiometer |
| X9C503DM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Potentiometer |
| X9C503P | 功能描述:IC DIGITAL POT 50K 100TP 8DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲(chǔ)器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9C503PI | 功能描述:IC DIGITAL POT 50K 100TP 8DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲(chǔ)器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9C503PIZ | 功能描述:IC XDCP 100-TAP 50K EE 8-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲(chǔ)器類型:易失 接口:6 線串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
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