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參數(shù)資料
| 型號(hào)： | XA3S700A-4FGG484I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 25/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3A 700K 484-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-3A XA |
| LAB/CLB數(shù)： | 1472 |
| 邏輯元件/單元數(shù)： | 13248 |
| RAM 位總計(jì)： | 368640 |
| 輸入/輸出數(shù)： | 372 |
| 門數(shù)： | 700000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA |
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XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
31
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load Conditions in Application
IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS
model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 26 (VT, RT, and VM). Do not confuse
VREF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth
parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in
the Xilinx development software as well as at the following link:
Delays for a given application are simulated according to its specific load conditions as follows:
1.
Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 9. Use
2.
Record the time to VM.
3.
Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS
model (including VREF, RREF, CREF, and VMEAS values) or capacitive value to represent the load.
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. Add (or subtract) the increase (or decrease) in delay to (or from) the appropriate
Output standard adjustment (Table 25) to yield the worst-case delay of the PCB trace.
DIFF_SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
DIFF_SSTL2_I
1.25
VREF – 0.5
VREF + 0.5
50
1.25
VREF
DIFF_SSTL2_II
1.25
VREF – 0.5
VREF + 0.5
50
1.25
VREF
DIFF_SSTL3_I
1.5
VREF – 0.5
VREF + 0.5
50
1.5
VREF
DIFF_SSTL3_II
1.5
VREF – 0.5
VREF + 0.5
50
1.5
VREF
Notes:
1.
Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 M when no parallel termination is required
VT – Termination voltage
2.
The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
3.
According to the PCI specification.
Table 26: Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard
(IOSTANDARD)
Inputs
Outputs
Inputs and
Outputs
VREF (V)
VL (V)
VH (V)
RT ()VT (V)
VM (V)
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| XA3S700A-4FGG484Q | 功能描述:IC FPGA SPARTAN-3A 700K 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3A XA 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XA3SD1800A | 制造商:XILINX 制造商全稱:XILINX 功能描述:XA Spartan-3A DSP Automotive FPGA Family Data Sheet |
| XA3SD1800A-4CSG484I | 功能描述:SPARTAN-3ADSP FPGA 1800K 484CSBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3A DSP XA 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XA3SD1800A-4CSG484Q | 功能描述:SPARTAN-3ADSP FPGA 1800K 484CSBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3A DSP XA 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
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