T<" />
參數(shù)資料
型號： XA3SD1800A-4FGG676Q
廠商： Xilinx Inc
文件頁數(shù)： 13/58頁
文件大?。?/td> 0K
描述： SPARTAN-3ADSP FPGA 1800K 676FBGA
產(chǎn)品培訓模塊： Extended Spartan 3A FPGA Family
標準包裝： 40
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 4160
邏輯元件/單元數(shù)： 37440
RAM 位總計： 1548288
輸入/輸出數(shù)： 519
門數(shù)： 1800000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
配用： 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
20
Hold Times
TIOICKP
Time from the active transition at the ICLK
input of the Input Flip-Flop (IFF) to the point
where data must be held at the Input pin. No
Input Delay is programmed.
LVCMOS25(3)
0
XA3SD1800A
–0.52
ns
XA3SD3400A
–0.56
ns
TIOICKPD
Time from the active transition at the ICLK
input of the Input Flip-Flop (IFF) to the point
where data must be held at the Input pin. The
Input Delay is programmed.
LVCMOS25(3)
1
XA3SD1800A
–1.40
ns
2
–2.11
ns
3
–2.48
ns
4
–2.77
ns
5
–2.62
ns
6
–3.06
ns
7
–3.42
ns
8
–3.65
ns
1
XA3SD3400A
–1.31
ns
2
–1.88
ns
3
–2.44
ns
4
–2.89
ns
5
–2.83
ns
6
–3.33
ns
7
–3.63
ns
8
–3.96
ns
Set/Reset Pulse Width
TRPW_IOB Minimum pulse width to SR control input on
IOB
–
All
1.61
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 23.
3.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 23. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 21: Sample Window (Source Synchronous)
Symbol
Description
Max
Units
TSAMP
Setup and hold
capture window of
an IOB flip-flop
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
Answer Record 30879
ps
Table 20: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
Description
Conditions
IFD_DELAY
_VALUE
Device
Speed Grade: -4
Units
Min
相關(guān)PDF資料
PDF描述
XC4VLX15-10FFG668C IC FPGA VIRTEX-4 LX 15K 668FCBGA
SST25WF020-40-5I-SAF-T IC FLASH SER 2MB 40MHZ SPI 8SOIC
25LC128T-I/SM IC EEPROM 128KBIT 10MHZ 8SOIC
XC6SLX100T-2FGG676C IC FPGA SPARTAN 6 101K 676FGGBGA
24FC256T-I/MS IC EEPROM 256KBIT 1MHZ 8TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XA3SD3400A 制造商:XILINX 制造商全稱:XILINX 功能描述:XA Spartan-3A DSP Automotive FPGA Family Data Sheet
XA3SD3400A-4CSG484I 功能描述:SPARTAN-3ADSP FPGA 3400K 484CSBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP XA 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XA3SD3400A-4FGG676I 功能描述:SPARTAN-3ADSP FPGA 3400K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP XA 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
X-A4A-300L 制造商:Leach International Corporation 功能描述:MID RANGE - Bulk
X-A4C-300M 制造商:Leach International Corporation 功能描述:MID RANGE - Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*