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參數(shù)資料
| 型號： | XA6SLX9-3FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPAG SPARTAN 6 9K 256FTGBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Spartan®-6 LX XA |
| LAB/CLB數(shù)： | 715 |
| 邏輯元件/單元數(shù)： | 9152 |
| RAM 位總計： | 589824 |
| 輸入/輸出數(shù)： | 186 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
XA Spartan-6 Automotive FPGA Family Overview
DS170 (v1.3) December 13, 2012
Product Specification
2
XA Spartan-6 FPGA Feature Summary
FPGA Device Package Combinations and Available I/Os
XA Spartan-6 FPGA package combinations with the available I/Os and GTP transceivers per package are shown in Table 2.
Due to the transceivers, the LX and LXT pinouts are not compatible.
Table 1: XA Spartan-6 FPGA Feature Summary by Device
Device
Logic
Cells(1)
Configurable Logic Blocks (CLBs)
DSP48A1
Slices(3)
Block RAM Blocks
CMTs(5)
Memory
Controller
Blocks
(Max)
Endpoint
Blocks for
PCI Express
Maximum
GTP
Transceivers
Total
I/O
Banks
Max
User
I/O
Slices(2)
Flip-Flops
Max
Distributed
RAM (Kb)
18 Kb(4)
Max (Kb)
XA6SLX4
3,840
600
4,800
75
8
12
216
2
0
4
132
XA6SLX9
9,152
1,430
11,440
90
16
32
576
2
0
4
200
XA6SLX16
14,579
2,278
18,224
136
32
576
2
0
4
232
XA6SLX25
24,051
3,758
30,064
229
38
52
936
2
0
4
266
XA6SLX45
43,661
6,822
54,576
401
58
116
2,088
4
2
0
4
320
XA6SLX75
74,637
11,662
93,296
692
132
172
3,096
6
2
0
4
328
XA6SLX100
101,261
15,822
126,576
976
180
268
4,824
6
2
0
4
326
XA6SLX25T
24,051
3,758
30,064
229
38
52
936
2
1
2
4
250
XA6SLX45T
43,661
6,822
54,576
401
58
116
2,088
4
2
1
4
296
XA6SLX75T
74,637
11,662
93,296
692
132
172
3,096
6
2
1
4
268
Notes:
1.
XA Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture.
2.
Each XA Spartan-6 FPGA slice contains four LUTs and eight flip-flops.
3.
Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator.
4.
Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.
5.
Each CMT contains two DCMs and one PLL.
Table 2: XA Spartan-6 Device-Package Combinations and Maximum Available I/Os
Package(1)
CSG225(2)
FTG256
CSG324
CSG484(3)
FGG484(3)
Size (mm)
13x13
17x17
15x15
19x19
23 x 23
Pitch (mm)
0.8
1.0
0.8
1.0
Device
User I/O
GTPs
User I/O
GTPs
User I/O
GTPs
User I/O
XA6SLX4
132
XA6SLX9
160
186
NA
200
XA6SLX16
160
186
NA
232
XA6SLX25
186
NA
226
NA
266
XA6SLX45
NA
218
NA
320
NA
316
XA6SLX75
NA
328
NA
280
XA6SLX100
NA
326
XA6SLX25T
2
190
2
250
XA6SLX45T
4
190
4
296
XA6SLX75T
4
268
Notes:
1.
XA Spartan-6 devices are available in Pb-free packages only.
2.
Memory controller block support is x8 on the XA6SLX9 and XA6SLX16 devices in the CSG225 package. There is no memory controller in the
XA6SLX4.
3.
These packages support two of the four memory controllers in the XA6SLX75, XA6SLX75T, and XA6SLX100 devices.
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